PVT-aware leakage reduction for on-die caches with improved read stability

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 1, 2006, Pages 170-178

  Kim, Ch ^a   Kim, Jae Joon ^a   Chang, Ik Joon ^a   Roy, K ^a  

^a University of Minnesota   (United States)

Author keywords

Architectural access behavior; Maximum leakage savings; On die SRAM caches; Overhead energy; Periodic sleep pulse; PVT aware leakage reduction; Read stability improvement; Run time leakage reduction technique; Self decay circuit; Sleep mode

Indexed keywords

LEAKAGE CURRENTS; NETWORKS (CIRCUITS); SELF ADJUSTING CONTROL SYSTEMS; STABILITY; STATIC RANDOM ACCESS STORAGE; SWITCHING CIRCUITS;

ARCHITECTURAL ACCESS BEHAVIOR; MAXIMUM LEAKAGE SAVINGS; ON-DIE SRAM CACHES; OVERHEAD ENERGY; PERIODIC SLEEP PULSE; PVT-AWARE LEAKAGE REDUCTION; READ STABILITY IMPROVEMENT; RUN-TIME LEAKAGE REDUCTION TECHNIQUE; SELF-DECAY CIRCUIT; SLEEP MODE;

CACHE MEMORY;

EID: 31344463249     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.859315     Document Type: Article

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