Process variation aware SRAM/cache for aggressive voltage-frequency scaling

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2009, Pages 911-916

  Sasan, Avesta ^a   Homayoun, Houman ^a   Eltawil, Ahmed ^a   Kurdahi, Fadi ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CYTOLOGY; DYNAMIC RANDOM ACCESS STORAGE; ELECTRIC POWER UTILIZATION; STATIC RANDOM ACCESS STORAGE; VOLTAGE SCALING;

AREA OVERHEAD; DYNAMIC POWER CONSUMPTION; LEAKAGE POWER CONSUMPTION; LOW VOLTAGE OPERATION; PERIPHERAL CIRCUITRY; PROCESS VARIATION; READ OPERATION; VOLTAGE FREQUENCY;

CELLS;

EID: 70350075819     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2009.5090795     Document Type: Conference Paper

References (18)

1. S. R. Nassif "Modeling and Analysis of manufacturing variation" in Proc. CICC, 2001 pp/ 223-228
2. S. Borkar, T. Karnik, et al., "Process Variation and impact on circuits and micro architectures," in Proc DAC 2003 pp338-342
3. S. Mukhopadhyay, H. Mahmoodi, K. Roy "Modeling of Failure Probability and Statistical Design of SRAM Array for Yield Enhancement in NanoScaled CMOS" CADICS Vol.24 NO. 12, DEC 2005
4. A. Bhavnagarwala, X. et al. " The impact of intrinsic device fluctuation on CMOS SRAM cell stability," IEEE J. Solid-State Circuits vol.36, no.4 pp 658-665 Apr 2001
5. H. Mahmoodi, at al.. "Modeling of failure probability and statistical design of SRAM array for yield enhancement in nano-scaled cmos," IEEE Trans CAD , 2003
6. Avesta Sasan (Mohammad A Makhzan), Amin Khajeh, Ahmed Eltawil, Fadi Kurdahi, "Limits of Voltage Scaling for Caches Utilizing Fault Tolerant Techniques". ICCD 2007.
7. S. E. Schuster, "Multiple word/bit line redundancy for semiconductor memories," IEEE J. Solid-State Circuits, vol. SC-13, no. 5, pp. 698-703, Oct. 1978.
8. M. Horiguchi, "Redundancy techniques for high-density DRAMS," in Proc. 2nd Annu. IEEE Int. Conf. Innovative Systems in Silicon, Oct. 1997, pp. 22-29.
9. A. Argawal, B. C. Paul, S Mukhopadhyay, K. Roy "Process Variation in Embedded Memories: Failure Analysis and Variation Aware Architecture." IEEE Journal of Solid State Cuircuits, VOL. 40, NO. 9, SEPTEMBER 2005
10. H. L. Kalter et al., "A 50-ns 16-Mb DRAM with a 10 ns data rate and on chip ECC," IEEE J. Solid-State Circuits, vol. 25, no. 5, pp. 1118-1128, Oct. 1990.
11. D. Weiss, J. J. Wuu, and V. Chin, "The on-chip 3-MB subarray-based third level cache on an itanium microprocessor," IEEE J. Solid-StateCircuits, vol. 37, no. 11, pp. 1523-1529, Oct. 1990.
12. S. Mukhopadhyay, et al., "Statistical design and optimization of SRAM cell for yield enhancement," in Proc. Int. Conf. Computer Aided Design (ICACD), Nov. 2004, pp. 10-13.
13. P. P. Shirvani and E. J. McCluskey, "PADded Cache: A New Fault-Tolerance Technique for Cache Memories", In Proc. Of 17th IEEE VLSI Test Symposium, pp.440-445, April 1999.
14. http://www.eas.asu.edu/∼ptm
15. Bhalerao, et al., " A CMOS Low Voltage Charge Pump" VSLID 2007
16. http://quid.hpl.hp.com:9082/cacti/
17. G. Sohi, "Cache Memory Organization to Enhance the Yield of High Performance VLSI Processors", IEEE Trans. Comp., vol.38(4), , pp.484-492, April 1989
18. Avesta Sasan (Mohammad A Makhzan), Houman Homayoun, Ahmed Eltawil, Fadi Kurdahi, "Architectural and Algorithm Level Fault Tolerant Techniques for Low Power High Yield Multimedia Devices". ICCD 2007.