Cache power reduction in presence of within-die delay variation using spare ways

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Trends in VLSI Technology and Design, ISVLSI 2008

Volumn , Issue , 2008, Pages 447-450

  Goudarzi, Maziar ^a   Matsumura, Tadayuki ^a   Ishihara, Tohru ^a  

^a KYUSHU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE POWER CONSUMPTION; DELAY VARIATIONS; POWER REDUCTIONS; TECHNOLOGY SCALING; VLSI TECHNOLOGIES; WITHIN-DIE;

TECHNOLOGY;

EID: 51849110333     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2008.19     Document Type: Conference Paper

References (11)

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