Adaptive SRAM memory for low power and high yield

26th IEEE International Conference on Computer Design 2008, ICCD

Volumn , Issue , 2008, Pages 176-181

  Mohammad, Baker ^a   Bijansky, Stephen ^a   Aziz, Adnan ^a   Abraham, Jacob ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

6T CELLS; AREA OVERHEADS; BIT LINES; COLUMN BASIS; DESIGN PHASE; FEATURE SIZES; FINE-GRAINED CONTROLS; FIXED VOLTAGES; HIGH YIELDS; LOW-POWER; MULTIPLE SUPPLY VOLTAGES; REAL-WORLD; SRAM MEMORIES; SUPPLY VOLTAGES; VOLTAGE ASSIGNMENTS; YIELD TARGETS;

DESIGN;

STATIC RANDOM ACCESS STORAGE;

EID: 62349095031     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2008.4751858     Document Type: Conference Paper

References (8)

1. S. Rusu, S. Tam, H. Muljono, D. Ayers, J. Chang, B. Cherkauer, J. Stinson, J. Benoit, R. Varada, J. Leung, et al., "A 65-nm Dual-Core Multithreaded Xeon Processor With 16-MB L3 Cache," IEEE Journal of Solid-State Circuits, 2007.
2. J. Massey, I. Microeletronics, and V. Essex Junction, "NBTI: What we know and what we need to know-A tutorial addressing the current understanding and challenges for the future," Integrated Reliability Workshop Final Report, 2004 IEEE International, pp. 199-211, 2004.
3. M. Yamaoka, N. Maeda, Y. Shinozaki, Y. Shimazaki, K. Nii, S. Shimada, K. Yanagisawa, and T. Kawahara, "90-nm Process-Variation Adaptive Embedded SRAM Modules With Power-Line-Floating Write Technique," IEEE Journal of Solid-State Circuits, 2006.
4. A. Hoefler, C. Henson, C.-N. Li, and D.-G. Lin, "Analysis of a Novel Electrically Programmable Active Fuse for Advanced CMOS SOI One-Time Programmable Memory Applications," Solid-State Device Research Conference, 2006.
5. P. Royannez, H. Dahan, F. Wagner, M. Streeter, M. Bouetel, L. Blasquez, J. Clasen, H. Semino, G. Scott, D. Pitts, et al., "90nm low leakage SoC design techniques for wireless applications," IEEE International Solid-State Circuits Conference, 2005.
6. K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Y. Wang, B. Zheng, and M. Bohr, "A 3-GHz 70mb SRAM in 65nm CMOS technology with integrated column-based dynamic power supply," IEEE International Solid-State Circuits Conference, 2005.
7. S. Mukhopadhyay, K. Kim, H. Mahmoodi, and K. Roy, "Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS," IEEE Journal of Solid-State Circuits, 2007.
8. M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Ohbayashi, S. Imaoka, H. Makino, Y. Yamagami, S. Ishikura, T. Terano, T. Oashi, et al., "A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations," IEEE International Solid-State Circuits Conference, 2007.