Process variation-aware adaptive cache architecture and management

IEEE Transactions on Computers

Volumn 58, Issue 7, 2009, Pages 865-877

  Mutyam, Madhu ^a   Wang, Feng ^b   Krishnan, Ramakrishnan ^c   Narayanan, Vijaykrishnan ^c   Kandemir, Mahmut ^c   Xie, Yuan ^c   Irwin, Mary Jane ^c  

^a INDIAN INSTITUTE OF TECHNOLOGY MADRAS   (India)

^b QUALCOMM INC   (United States)

^c The Pennsylvania State University   (United States)

Author keywords

Address prediction; Cache; Process variation; Superscalar processors

Indexed keywords

ACCESS LATENCY; ADDRESS PREDICTION; CACHE; CACHE ACCESS; CACHE ARCHITECTURE; CACHE MANAGEMENT POLICIES; CRITICAL PROCESS PARAMETERS; DESIGN METHODOLOGY; FUTURE DESIGNS; HARDWARE COMPONENTS; MEMORY COMPONENT; MINIMUM-SIZED TRANSISTORS; NONUNIFORM; ON-CHIP DATA CACHE; PROCESS VARIATION; SUPERSCALAR PROCESSORS; WORST CASE DESIGN; WORST CASE SCENARIO;

DESIGN;

EID: 67649855147     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2009.30     Document Type: Article

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