Performance and modeling of Si-nanocrystal double-layer memory devices with high-k control dielectrics

IEEE Transactions on Electron Devices

Volumn 59, Issue 4, 2012, Pages 933-940

  Gay, G ^a   Molas, G ^a   Bocquet, M ^a,b   Jalaguier, E ^a   Gely M ^a   Masarotto, L ^a   Colonna, J P ^a   Grampeix, H ^a   Martin, F ^a   Brianceau, P ^a   Vidal, V ^a   Kies, R ^a   Baron, T ^c   Ghibaudo, G ^b   De Salvo, B ^a  

^a MINATEC   (France)

^b IMEP LAHC   (France)

^c CNRS   (France)

Author keywords

HfAlO; high k; interpoly; nonvolatile memory devices; silicon nanocrystals (Si ncs)

Indexed keywords

HFALO; HIGH-K; INTER-POLY; NONVOLATILE MEMORY DEVICES; SILICON NANOCRYSTALS (SI-NCS);

ACTIVATION ENERGY; ELECTRON TUNNELING; EQUIPMENT; NANOCLUSTERS; NONVOLATILE STORAGE;

SILICON;

EID: 84859213658     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2012.2182769     Document Type: Article

References (24)

1. S. Lombardo, B. De Salvo, C. Gerardi, and T. Baron, "Silicon nanocrystal memories," Microelectron. Eng., vol. 72, no. 1-4, pp. 388-394, Apr. 2004.
2. G. Chindalore, J. Yater, H. Gasquet, M. Suhail, S. Kang, C. M. Hong, N. Ellis, G. Rinkenberger, J. Shen, M. Herrick, W. Malloch, R. Syzdek, K. Baker, and K. Chang, "Embedded split-gate Flash memory with silicon nanocrystals for 90 nm and beyond," in VLSI Symp. Tech. Dig., 2008, pp. 136-137.
3. S. Jacob, B. De Salvo, L. Perniola, G. Festes, S. Bodnar, R. Coppard, J. F. Thiery, T. Pate-Cazal, C. Bongiorno, S. Lombardo, J. Dufourcq, E. Jalaguier, T. Pedron, F. Boulanger, and S. Deleonibus, "Integration of CVD silicon nanocrystals in a 32 Mb NOR Flash memory," Solid State Electron., vol. 52, no. 9, pp. 1452-1459, Sep. 2008.
4. C. Gerardi, G. Molas, G. Albini, E. Tripiciano, M. Gely, A. Emmi, O. Fiore, E. Nowak, D. Mello, M. Vecchio, L. Masarotto, R. Portoghese, B. De Salvo, S. Deleonibus, and A.Maurelli, "Performance and reliability of a 4Mb Si nanocrystal NOR Flash memory with optimized 1T memory cells," in IEDM Tech. Dig., 2008, pp. 821-824.
5. G. Molas, M. Bocquet, J. Buckley, J. P. Colonna, L. Masarotto, H. Grampeix, F. Martin, V. Vidal, A. Toffoli, P. Brianceau, L. Vermande, P. Scheiblin, M. Gely, A. M. Papon, G. Auvert, L. Perniola, C. Licitra, T. Veyron, N. Rochat, C. Bongiorno, S. Lombardo, B. De Salvo, and S. Deleonibus, "Thorough investigation of Si-nanocrystal memories with high-k interpoly dielectrics for sub-45 nm node Flash NAND applications," in IEDM Tech. Dig., 2007, pp. 453-456.
6. J. Dufourcq, S. Bodnar, G. Gay, D. Lafond, P. Mur, G. Molas, J. P. Nieto, L. Vandroux, L. Jodin, F. Gustavo, and T. Baron, "High density platinum nanocrystals for non-volatile memory applications," Appl. Phys. Lett., vol. 92, no. 7, p. 073 102, Feb. 2008.
7. P. K. Singh, R. Hofmann, K. K. Singh, N. Krishna, and S. Mahapatra, "Performance and reliability of Au and Pt single-layer metal nanocrystal Flash memory under NAND (FN/FN) operation," IEEE Trans. Electron. Devices, vol. 56, no. 9, pp. 2065-2072, Sep. 2009.
8. S. K. Samanta, Z. Y. L. Tan, W. J. Yoo, G. Samudra, and S. Lee, "Selfassembled tungsten nanocrystals in high-k dielectric for nonvolatile memory application," J. Vac. Sci. Technol. B, vol. 23, no. 6, p. 2278, Nov./Dec. 2005.
9. C. Lee, J. Meteer, V. Narayanan, and E. C. Kan, "Self-assembly of metal nanocrystals on ultrathin oxide for nonvolatile memory applications," J. Electron. Mater., vol. 34, no. 1, pp. 1-11, Jan. 2005.
10. P. K. Singh, K. K. Singh, R. Hofmann, K. Armstrong, N. Krishna, and S. Mahapatra, "Au nanocrystal Flash memory reliability and failure analysis," in Proc. 15th Int. Symp. Phys. Failure Anal. Integr. Circuits, 2008, pp. 1-5.
11. R. Ohba, N. Sugiyama, K. Ushida, J. Koga, and A. Toriumi, "Nonvolatile Si quantum memory with self-aligned doubly-stacked dots," IEEE Trans. Electron Devices, vol. 49, no. 8, pp. 1392-1398, Aug. 2008.
12. T. Z. Lu, M. Alexe, R. Scholz, V. Talelaev, and M. Zacharias, "Multilevel charge storage in silicon nanocrystal multilayers," AIP Appl. Phys. Lett., vol. 87, no. 20, p. 202 110, Nov. 2005.
13. Z. Zhang, L. Wang, P. Mao, L. Pan, and J. Xu, "Electrical properties of multilayer silicon nano-crystal nonvolatile memory," in Proc. ICSICT, 2008, pp. 962-965.
14. J. P. Colonna, G. Molas, M. Gely, M. Bocquet, E. Jalaguier, B. De Slavo, H. Grampeix, P. Brianceau, K. Yckache, A. Papon, G. Auvert, C. Bongiorno, and S. Lombardo, "Realization of hybrid silicon core/silicon nitride shell nanodots by LPCVD for NVM application," in Proc. Mater. Res. Soc. Symp. Proc., Warrendale, PA, 2008, vol. 1071, p. 1071-F02-02.
15. 2 and SiOxNy substrates for microelectronics devices," J. Cryst. Growth, vol. 209, no. 4, pp. 1004-1008, Feb. 2000.
16. G. Molas, M. Bocquet, J. Buckley, H. Grampeix, M. Gély, J.-P. Colonna, C. Licitra, N. Rochat, T. Veyront, X. Garros, F. Martin, P. Brianceau, V. Vidal, C. Bongiorno, S. Lombardo, B. De Salvo, and S. Deleonibus, "Investigation of hafnium-aluminate alloys in view of integration as interpoly dielectrics of future Flash memories," Solid State Electron., vol. 51, no. 11/12, pp. 1540-1546, Nov./Dec. 2007.
17. T. C. Chang, S. T. Yan, P. T. Liu, C. W. Chen, H. H. Wu, and S. M. Sze, "Quasisuperlattice storage: A concept of multilevel charge storage," J. Electrochem. Soc., vol. 151, no. 12, pp. G805-G808, Oct. 2004.
18. L. W. Yu, K. J. Chen, H. L. Ding, J. Xu, K. Liu, W. Li, X. Wang, and X. F. Huang, "Modeling and simulation for the enhancement of electron storage in a stacked multilayer nanocrystallite silicon floating gate memory," J. Appl. Phys., vol. 102, no. 1, p. 014 501, Jul. 2007.
19. 3-TaN) cell technology," in IEDM Tech. Dig., 2006, pp. 1-4.
20. R. A. Rao, R. F. Steimle, M. Sadd, C. T. Swift, B. Hradsky, S. Straub, T. Merchant, M. Stoker, S. G. H. Anderson, M. Rossow, J. Yater, B. Acred, K. Harber, E. J. Prinz, B. E. White, Jr., and R. Muralidhar, "Silicon nanocrystal based memory devices for NVM and DRAM applications," Solid State Elecron., vol. 48, no. 9, pp. 1463-1473, Sep. 2004.
21. 4/HfSiON stack for improved retention," in Proc. NVSMW ICMTD, 2006, pp. 50-51.
22. B. De Salvo, G. Ghibaudo, G. Pananakakis, P. Masson, T. Baron, N. Buffet, A. Fernandes, and B. Guillaumot, "Experimental and theoretical investigation of nano-crystal and nitride-trap memory devices," IEEE Trans. Electron Devices, vol. 48, no. 8, pp. 1789-1799, Aug. 2001.
23. 2/Ta2O3 dielectrics with oxide scaling," Microclectron. Eng., vol. 48, no. 1-4, pp. 295-298, Sep. 1999.
24. K. Schuegraf, C. King, and C. Hu, "Ultra thin silicon dioxide leakage current and scaling limit," in VLSI Symp. Tech. Dig., 1992, pp. 18-19.