Erratum to "Integration of CVD silicon nanocrystals in a 32 Mb NOR flash memory" [Solid State Electronics 52(9) (2008) 1452-1459] (DOI:10.1016/j.sse.2008.04.032);Integration of CVD silicon nanocrystals in a 32 Mb NOR flash memory

Solid-State Electronics

Volumn 52, Issue 9, 2008, Pages 1452-1459

  Jacob, S ^a,b   De Salvo, B ^b   Perniola, L ^b   Festes, G ^a   Bodnar, S ^a   Coppard, R ^a   Thiery, J F ^a   Pate Cazal, T ^a   Bongiorno, C ^c   Lombardo, S ^c   Dufourcq, J ^a   Jalaguier, E ^b   Pedron, T ^a   Boulanger, F ^b   Deleonibus, S ^b  

^a ATMEL Rousset   (France)

^b CEA GRENOBLE   (France)

^c CNR IMM   (Italy)

Author keywords

Flash memory; NOR; Silicon nanocrystals

Indexed keywords

CHEMICAL VAPOR DEPOSITION; NANOCLUSTERS; NANOCRYSTALS; SILICON; THRESHOLD VOLTAGE;

CHEMICAL VAPOR DEPOSITIONS (CVD); DEPOSITION CONDITIONS; INTEGRATION SCHEME; NOR FLASH MEMORY; RELIABILITY CHARACTERISTICS; SILICON NANOCRYSTALS; TECHNOLOGY PLATFORMS; THRESHOLD VOLTAGE DISTRIBUTION;

FLASH MEMORY;

EID: 50349088886     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2008.10.001     Document Type: Erratum

References (9)

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3. Steimle R.F., et al. Integration of silicon nanocrystals into a 6 V 4 Mb nonvolatile memory array. Proc NVSMW 73 (2004)
4. Lombardo S., et al. Distribution of the threshold voltage window in nanocrystal memories with Si dots formed by chemical vapor deposition: effect of partial self-ordering. Proc NVSMW 69 (2004)
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7. De Salvo B., et al. Experimental and theoretical investigation of nano-crystal and nitride-trap memory devices. IEEE Trans Electron Dev 48 (2001) 1789
8. Swift C.T., et al. Gate disturb reduction in a silicon nanocrystal flash EEPROM by means of natural threshold voltage reduction. Proc NVSMW (2006)
9. Perniola L., et al. Modeling of the programming window distribution in multinanocrystal memories. IEEE Trans Nanotechnol 2 4 (2003)