Sensor network-on-chip

2007 International Symposium on System-on-Chip Proceedings, SOC

Volumn , Issue , 2007, Pages

  Varatkar, Girish V ^a   Narayanan, Sriram ^a   Shanbhag, Naresh R ^a   Jones, Douglas ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CONSERVATION; ELECTRIC NETWORK TOPOLOGY; ENERGY CONSERVATION; ENERGY EFFICIENCY; ERRORS; INTEGRATED CIRCUITS; PROGRAMMABLE LOGIC CONTROLLERS; SENSORS; SIGNAL PROCESSING; STANDARDS; TECHNOLOGY; TECHNOLOGY TRANSFER;

CDMA 2000; CMOS PROCESS TECHNOLOGY; CODE ACQUISITION; DESIGNING ROBUST; DETECTION PROBABILITIES; ENERGY-EFFICIENT; ESTIMATION PROBLEMS; INTERNATIONAL SYMPOSIUM; NETWORK ON CHIPS; NETWORK-ON-A-CHIP; NON-IDEALITIES; POWER SAVINGS; PROCESS VARIATIONS; STATISTICAL SIGNAL PROCESSING; SYSTEM ON CHIPS; TIMING ERRORS;

SENSOR NETWORKS;

EID: 48149087451     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSOC.2007.4427447     Document Type: Conference Paper

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