A cost-effective dependable microcontroller architecture with instruction-level rollback for soft error recovery

Proceedings of the International Conference on Dependable Systems and Networks

Volumn , Issue , 2007, Pages 256-265

  Sakata, Teruaki ^a   Hirotsu, Teppei ^a   Yamada, Hiromichi ^a   Kataoka, Takeshi ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONIC DESIGN AUTOMATION (EDA); MICROCONTROLLER ARCHITECTURE; RANDOM LOGIC CIRCUITS;

AUTOMATION; COST EFFECTIVENESS; ERROR DETECTION; OPTIMIZATION; RANDOM ACCESS STORAGE; SOFTWARE ARCHITECTURE;

MICROCONTROLLERS;

EID: 36048961837     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSN.2007.5     Document Type: Conference Paper

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