A study of cognitive resilience in a JPEG compressor

Proceedings of the International Conference on Dependable Systems and Networks

Volumn , Issue , 2008, Pages 32-41

  Nowroth, Damian ^a   Polian, Ilia ^a   Becker, Bernd ^a  

^a UNIVERSITY OF FREIBURG   (Germany)

Author keywords

Cognitive resilience; Error tolerance; Imaging applications; Selective hardening

Indexed keywords

APPLICATIONS; BRAIN; COGNITIVE SYSTEMS; COMPRESSORS; ERROR CORRECTION; ERRORS; HARDENING; NETWORK PROTOCOLS; SENSOR NETWORKS;

COGNITIVE RESILIENCE; ERROR TOLERANCE; IMAGING APPLICATIONS; SELECTIVE HARDENING;

ERROR ANALYSIS;

EID: 53349107590     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSN.2008.4630068     Document Type: Conference Paper

References (40)

1. P.E. Dodd and L.W. Massengill. Basic mechanisms and modeling of single-event upset in digital microelectronics, IEEE Trans. on Nuclear Science, 50(3):583-602, 2003.
2. H.T. Nguyen and Y. Yagil. A systematic approach to SER estimation and solutions. In Int'l Reliability Physics Symp., pages 60-70, 2003.
3. P. Shivakumar, M. Kistler, W. Keckler, D. Burger, and L. Alvisi. Modeling the effect of technology trends on the soft error rate of combinational logic. In Int'l Conf. on Dependable Systems and Networks, pages 389-398, 2002.
4. N. Seifert, X. Zhu, and L.W. Massengill. Impact of scaling on soft-error rates in commercial microprocessors. IEEE Trans. on Nuclear Science, 49(6):3100-3106. 2002.
5. I. Polian, J.P. Hayes, S. Kundu, and B. Becker. Transient fault characterization in dynamic noisy environments. In Int'l Test Conf., 2005.
6. R. Baumann. Soft errors in advanced computer systems. IEEE Design & Test. 22(3):258-266, 2005.
7. K. Mohanram and N. Touba. Partial error masking to reduce soft error failure rate in logic circuits. In Int'l Symp. on Defect and Fault Tolerance, pages 433-440, 2003.
8. K. Mohanram and N.A. Touba. Cost-effective approach for reducing soft error failure rate in logic circuits. In Int'l Test Conf. pages 893-901, 2003.
9. C. Zhao, S. Dey, and X. Bai, Soft-spot analysis: Targeting compund noise effects in nanometer circuits. IEEE Design & Test of Comp., 22(4):362-375, 2005.
10. A.K. Nieuwland, S. Jasarevic, and G. Jerin. Combinational logic soft error analysis and protection. In Int'l On-line Test Symp., 2006.
11. J.P. Hayes, I. Polian, and B. Becker. An analysis framework for transient-error tolerance. In VLSI Test Symp., pages 249-255, 2007.
12. S.A. Seshia, W. Li, and S. Mitra. Verification-guided soft error resilience. In Design, Automation and Test in Europe Conf., 2007.
13. M. Zhang, S. Mitra, T.M. Mak, N. Seifert, N.J. Wang, Q. Shi, K.S. Kim, N.R. Shanbhag, and S.J. Patel. Sequential element design with built-in soft error resilience. IEEE Trans. on VLSI, 14(12): 1368-1378. 2006.
14. M. Breuer. Multi-media applications and imprecise computation. In EUROMICRO, pages 2-7, 2005.
15. I. Chong and A. Ortega. Hardware testing for error tolerant multimedia compression based on linear transforms. In Int'l Symp. on Defect and Fault Tolerance in VLSI Systems, 2005.
16. II. Chung and A. Ortega. Analysis and testing for error tolerant motion estimation. In Int'l Symp. on Defect and Fault Tolerance in VLSI Systems, 2005.
17. I. Chong, H. Cheong, and A. Ortega. New quality metric for multimedia compression using faulty hardware. In Int'l Workshop on Video Processing and Quality Metrics for Consumer Electronics, 2006.
18. I. Polian. D. Nowroth, and B. Becker. Identification of critical errors in imaging applications. In Int'l On-line Test Symp., pages 201-202, 2007. (Poster).
19. V. Bhaskaran and K. Konstantinides. Image and Video Compression Standards: Algorithms and Architectures. Kluwer Academic Publishers, kluwer international series in engineering and computer science edition, 1995.
20. D.P. Siewiorek and R.S. Swarz. Reliable Computer Systems - Design and Evaluation. Digital Press, 1992.
21. P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, and M. Violante. An FPGA-based approach for speeding-up fault injection campaigns on safety-critical circuits. Jour. of Electronic Testing: Theory and Applications, 18(3):261-271, 2002.
22. S. Kundu, M.D.T. Lewis, I. Polian, and B. Becker. A soft error emulation system for logic circuits. In Conf on Design of Circuits and Integrated Systems, page 137, 2005.
23. N.J. Wang. J. Quek, T.M. Rafaez, and S.J. Patel. Characterizing the effects of transient faults on a high-performance processor pipeline. In Int'l Conf. on Dependable Systems and Networks. 2004.
24. C. Weaver, J. Emer, S.S. Mukherjee, and S.K. Reinhardt. Techniques to reduce the soft error rate of a high-performance microprocessor. In Int'l Symp. On Comp. Architecture, pages 264-275, 2004.
25. X. Li and D. Yeung. Application-level correctness and its impact on fault tolerance. In Int'l Symp. on High Performance Computer Architecture, pages 181-192, 2007.
26. J.W.S. Liu, W.-K. Shin, K.-J. Lin, R. Bettati, and J.-Y. Chung. Imprecise computations. Proc. of the IEEE, 82(1):83-94, 1994.
27. I. Polian, B. Becker, M. Nakasato, S. Ohtake, and H. Fujiwara. Period of grace: A new paradigm for efficient soft error hardening. In GI/ITG Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen ", 2006.
28. Y. Wang, S. Wenger, J. Wen, and A.K. Katsaggelos. Error resilient video coding techniques. IEEE Signal Process. Mag., 17(4):61-82, 2000.
29. W.-Y. Rung, C-S. Rim, and C.-C.J. Ruo. Spatial and temporal error concealment techniques for video transmission over noisy channels. Trans. Circuits and Systems for Video Tech., 16(7):789-802, 2006.
30. Z. Wang and A.C. Bovik. Modern Image Quality Assessment. Morgan and Claypool Publishers. 2006.
31. Z. Wang. A. C. Bovik, H. R. Sheikh, and E. P. Simoncelli. Image quality assessment: From error visibility to structural similarity. In IEEE Transactions on Image Processing, volume 13, pages 600-612, April 2004.
32. SSIM C++ implementation. http://mehdi.rabah.tree.fr/SSIM/, Juni 2007.
33. V. Joshi, R.R. Rao, D. Blaauw, and D. Sylvester. Logic SER reduction through flip flop redesign. In Int'l Symp. on Quality Electronic Design, pages 611-616, 2006.
34. JPEG hardware compressor - opencores.org. http://www.opencores.org/ projects.cgi/web/jpeg/overview, Februar 2007.
35. J. Arlat, M. Aguera, L. Amai, Y. Crouzet, J.-C. Fabre, E. Martins, and D. Powell. Fault injection for dependability validation: a methodology and some applications. In Trans. on Soft. Eng., volume 16, pages 166-182, 1990.
36. H. Madeira, M. Rela, and J.G. Silva. RIFLE: A general purpose pin-level fault injector. In Proc. First European Dependable Computing Conference (EDCC-1), pages 199-216, Berlin, 1994.
37. E. Czeck and D. Siewiorek. Effects on transient gate-level faults on program behavior. In Proc. 20th Symp. on Fault Tolerant Computing (FTCS-20), pages 236 243, Newcastle Upon Tyne, 1990.
38. G. Choi. R. Iyer, and V. Carreno. Simulated fault injection: A methodology to evaluate fault tolerant microprocessor architectures. In IEEE Trans. on Reliability, volume 39, pages 486-490, 1990.
39. E. Jenn, J. Arlat, M. Rimen, J. Ohlsson, and J. Karlsson. Fault injection into VHDL models: The MEFISTO tool. In Proc. 24th Symp. on Fault Tolerant Computing (FTCS-24), pages 66-75, Austin, USA, 1994.
40. V. Sieh, O. Tschache, and F. Balbach. VERIFY: Evaluation of reliability using VIIDL-models with embedded fault descriptions. In 27th International Symposium on Fault-Tolerant Computing (FTCS '97), pages 32-36, Seattle, USA, 1997.