Trades-off between lithography line edge roughness and error-correcting codes requirements for NAND Flash memories

Microelectronics Reliability

Volumn 52, Issue 3, 2012, Pages 525-529

  Poliakov, Pavel ^a,b   Blomme, Pieter ^a   Pret, Alessandro Vaglio ^a,b   Corbalan, Miguel Miranda ^a   Gronheid, Roel ^a   Verkest, Diederik ^a,c   Houdt, Jan Van ^a   Dehaene, Wim ^a,b  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c VRIJE UNIVERSITEIT BRUSSEL   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

BIT-ERRORS; DATA ERRORS; DATA INTEGRITY; ERROR CORRECTING CODE; EXTREME ULTRAVIOLETS; LINE EDGE ROUGHNESS; LITHOGRAPHY PROCESS; MEMORY ARRAY; MEMORY DESIGN; MOORE'S LAW; NAND FLASH MEMORY; PROBABILISTIC COMPUTING; TRANSISTOR STRUCTURE;

INFORMATION THEORY; NAND CIRCUITS;

LITHOGRAPHY;

EID: 84857374255     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2011.09.037     Document Type: Article

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