Multibit error-correction methods for latency-constrained flash memory systems

IEEE Transactions on Device and Materials Reliability

Volumn 10, Issue 1, 2010, Pages 33-39

  Ankolekar, Priyanka P ^a   Isaac, Roger ^b   Bredow, Jonathan W ^a  

^a The University of Texas at Arlington   (United States)

^b Silicon Image Inc   (United States)

Author keywords

Error correction codes (ECCs); Flash memory; Low latency

Indexed keywords

BCH CODE; BLOCK SIZES; CORRECTING CAPACITY; DIE AREA; ECC ALGORITHMS; ECC SCHEME; ERROR CORRECTION CODES; ERROR-CORRECTION CODES (ECCS); EXECUTE IN PLACES; HAMMING CODE; HARDWARE IMPLEMENTATIONS; LOW LATENCY; MULTI-BIT ERROR; MULTI-BITS; NOR FLASH; READ ACCESS TIME; SINGLE-BIT;

ALGORITHMS; ERROR CORRECTION; HARDWARE; WIRELESS SENSOR NETWORKS;

FLASH MEMORY;

EID: 77949390552     PISSN: 15304388     EISSN: 15304388     Source Type: Journal    
DOI: 10.1109/TDMR.2009.2031171     Document Type: Article

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