A zeroing cell-to-cell interference page architecture with temporary LSB storing and parallel MSB program scheme for MLC NAND flash memories

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 4, 2008, Pages 919-927

  Park, Ki Tae ^b   Kang, Myounggon ^b   Kim, Doogon ^b   Hwang, Soon Wook ^b   Choi, Byung Yong ^b   Lee, Yeong Taek ^b   Kim, Changhyun ^a,b   Kim, Kinam ^a,b  

^a IEEE

^b SAMSUNG Electronics   (South Korea)

Author keywords

Bitline voltage modulation ISPP; Cell to cell interference; NAND flash; Page architecture; Parallel MSB programming; Temporary LSB storing

Indexed keywords

COMPUTER PROGRAMMING; FLASH MEMORY; PARALLEL PROCESSING SYSTEMS; VOLTAGE CONTROL;

BITLINE VOLTAGE MODULATION; CELL TO CELL INTERFERENCE; MEMORY ARRAYS; PAGE ARCHITECTURE;

NAND CIRCUITS;

EID: 41549125910     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.917558     Document Type: Conference Paper

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