Pulsed-latch circuits: A new dimension in ASIC design

IEEE Design and Test of Computers

Volumn 28, Issue 6, 2011, Pages 50-57

  Shin, Youngsoo ^a   Paik, Seungwhun ^b  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b SYNOPSYS INC   (United States)

Author keywords

design and test; high performance; low power; pulsed latch; pulsed latch ASIC methodology

Indexed keywords

DESIGN AND TESTS; HIGH PERFORMANCE; LOW POWER; PULSED LATCH; PULSED-LATCH ASIC METHODOLOGY;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DESIGN; INTEGRATED CIRCUITS; LOW POWER ELECTRONICS;

FLIP FLOP CIRCUITS;

EID: 80053629025     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2011.24     Document Type: Article

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