A robust pulsed flip-flop and its use in enhanced scan design

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2009, Pages 97-102

  Kumar, Rajesh ^a   Bollapalli, Kalyana C ^a   Garg, Rajesh ^b   Soni, Tarun ^a   Khatri, Sunil P ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AT-SPEED; DELAY FAULTS; DETECTION CAPABILITY; ENHANCED SCAN; ENHANCED SCAN FLIP-FLOPS; FLIP-FLOP DESIGNS; LAYOUT AREA; MASTER-SLAVE; MONTE CARLO SIMULATION; NANOMETER TECHNOLOGY; POWER DISSIPATION; PROCESS VARIATION; SCAN DESIGNS; TEST VECTORS;

COMPUTER SIMULATION; DESIGN; FAULT DETECTION; MONTE CARLO METHODS; SCANNING; TIME MEASUREMENT;

FLIP FLOP CIRCUITS;

EID: 77649164365     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2009.5413168     Document Type: Conference Paper

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