A multigigahertz clocking scheme for the Pentium® 4 microprocessor

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 11, 2001, Pages 1647-1653

  Kurd, Nasser A ^a,b   Barkatullah, Javed S ^a,b   Dizon, Rommel O ^b   Fletcher, Thomas D ^b   Madland, Paul D ^a,b  

^a IEEE   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Clock distribution; Clock generation; Glitch protection; Jitter reduction; Skew optimization; Source synchronous bus

Indexed keywords

CLOCK DISTRIBUTION NETWORK; GLITCH PROTECTION; MULTIGIGAHERTZ CLOCKING SCHEME; PENTIUM 4 MICROPROCESSOR;

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; JITTER; MICROPROCESSOR CHIPS; OPTIMIZATION; PERSONAL COMPUTERS; PHASE LOCKED LOOPS; SEMICONDUCTING SILICON; TRANSISTORS;

TIMING CIRCUITS;

EID: 0035505541     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.962284     Document Type: Article

References (7)

1. Multigigahertz clocking scheme for Intel® Pentium® 4 microprocessor
2. A 0.18-μm CMOS IA-32 microprocessor with a 4-GHz integer execution unit
3. Two novel fully complementary self-biased CMOS differential amplifiers
4. Differential CMOS circuits for 622-MHz/933-MHz clock and data recovery applications
5. A 0.35-μm CMOS 3 880-MHz PLL N/2 clock multiplier and distribution network with low jitter for microprocessors
6. Clock generation and distribution for the first IA-64 microprocessor
7. Backside infrared probing for static voltage drop and dynamic timing measurements