Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 10, 1996, Pages 1237-1248

  Sapatnekar, Sachin S ^a   Deokar, Rahul B ^a  

^a Tnwa State TTnivercitv ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; COMPUTATIONAL COMPLEXITY; EQUIVALENCE CLASSES; FLIP FLOP CIRCUITS; LOGIC GATES; OPTIMIZATION; PROBLEM SOLVING;

CLOCK SKEW; RETIMING; RETIMING SKEW EQUIVALENCE;

COMPUTER AIDED DESIGN;

EID: 0030260869     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.541443     Document Type: Article

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