Clock scheduling and clocktree construction for high performance ASICs

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2003, Pages 232-239

  Held, Stephan ^a   Korte, Bernhard ^a   Maßberg, Jens ^a   Ringe, Matthias ^b   Vygen, Jens ^a  

^a UNIVERSITY OF BONN   (Germany)

^b IBM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CONSTRAINT THEORY; LINEAR PROGRAMMING; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; QUADRATIC PROGRAMMING; SCHEDULING; VLSI CIRCUITS;

CLOCK SCHEDULING; CLOCKTREE CONSTRUCTION;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0348040124     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iccad.2003.159695     Document Type: Conference Paper

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