3-D nFPGA: A reconfigurable architecture for 3-D CMOS/nanomaterial hybrid digital circuits

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 54, Issue 11 SPEC. ISS., 2007, Pages 2489-2501

  Dong, Chen ^a   Chen, Deming ^a   Haruehanroengra, Sansiri ^b   Wang, Wei ^b  

^a United States of America   (United States)

^b Indiana University Purdue University Indianapolis   (United States)

Author keywords

3 D integration; Nanoelectronics; Nanotube; Nanowire; Performance; Reconfigurable logic

Indexed keywords

BENCHMARKING; CARBON NANOTUBES; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; FAULT TOLERANCE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); NANOELECTRONICS; NANOTUBES; NANOWIRES; RECONFIGURABLE ARCHITECTURES; THREE DIMENSIONAL INTEGRATED CIRCUITS; TIMING CIRCUITS;

3-D INTEGRATION; CARBON NANOTUBE BUNDLE; DESIGN AUTOMATIONS; FPGA ARCHITECTURES; NANO-SCALE MATERIALS; PERFORMANCE; PROPOSED ARCHITECTURES; RECONFIGURABLE LOGIC;

RECONFIGURABLE HARDWARE;

EID: 51949107529     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2007.907844     Document Type: Article

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