3-D nFPGA: A reconfigurable architecture for 3-D CMOS/nanomaterial hybrid digital circuits

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 54, Issue 11 SPEC. ISS., 2007, Pages 2489-2501

  Dong, Chen ^a   Chen, Deming ^a   Haruehanroengra, Sansiri ^b   Wang, Wei ^b  

^a University of Illinois at Urbana Champaign   (United States)

^b Indiana University Purdue University Indianapolis   (United States)

Author keywords

3 D integration; Nanoelectronics; Nanotube; Nanowire; Performance; Reconfigurable logic

Indexed keywords

BENCHMARKING; CARBON NANOTUBES; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; FAULT TOLERANCE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); NANOELECTRONICS; NANOTUBES; NANOWIRES; RECONFIGURABLE ARCHITECTURES; THREE DIMENSIONAL INTEGRATED CIRCUITS; TIMING CIRCUITS;

3-D INTEGRATION; CARBON NANOTUBE BUNDLE; DESIGN AUTOMATIONS; FPGA ARCHITECTURES; NANO-SCALE MATERIALS; PERFORMANCE; PROPOSED ARCHITECTURES; RECONFIGURABLE LOGIC;

RECONFIGURABLE HARDWARE;

EID: 51949107529     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2007.907844     Document Type: Article

References (38)

1. C. Ababei, P. Maidee, and K. Bazargan, "Exploring potential benefits of 3-D FPGA integration," in Field Programmable Logic and Application Berlin, Germany: Springer, 2004, vol. 3203, pp. 874-880.
2. E. Ahmed and J. Rose, "The effect of LUT and cluster size on deep-submicron FPGA performance and density," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 3, pp. 288-298, Mar. 2004.
3. M. D. Austin et al., "Fabrication of 5-nm linewidth and 14-nm pitch features by nanoimprint lithography," Appl. Phys. Lett., vol. 84, no. 26, pp. 5299-5301, 2004.
4. K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat, "3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration," Proc. IEEE, vol. 89, no. 5, pp. 602-633, May 2001.
5. V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for Deep-Submicron FPGAs. Norwell, MA: Kluwer, Feb. 1999.
6. D. Chen and J. Cong, "DAOmap: A depth-optimal area optimization mapping algorithm for FPGA designs," in Proc. IEEE Int. Conf. Computer-Aided Design, Nov. 2004, pp. 752-759.
7. Y. Chen et al., "Nanoscale molecular-switch crossbar circuits," Nanotechnology, vol. 14, pp. 462-468, 2003.
8. S. Chiricescu, M. Leeser, and M. M. Vai, "Design and analysis of a dynamically reconfigurable three-dimensional FPGA," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 9, no. 1, pp. 186-196, Feb. 2001.
9. W. R. Davis et al., "Demystifying 3-D ICs: The pros and cons of going vertical," IEEE Design Test. Comput., vol. 22, no. 6, pp. 498-510, Jun. 2005.
10. S. C. Goldstein and M. Budiu, "NanoFabric: Spatial computing using molecular electronics," in Proc. Int. Symp. Comput. Arch., 2001, pp. 178-189.
11. A. DeHon, "Nanowire-based programmable architectures," ACM J. Emerging Technol. Comput. Syst., vol. 1, no. 2, pp. 109-162, 2005.
12. B. Gojman et al., "3-D nanowire-based programmable logic," in Proc. Nanonet Conf., Lausanne, Switzerland, Sep. 2006, pp. 1-5.
13. C. Dong and W. Wang, "Exploring carbon nanotubes and NiSi nanowires as on-chip interconnections," in Proc. ISCAS'06, Kos, Greece, May 2006, pp. 3510-3513.
14. A. Gayasen, N. Vijaykrishana, and M. J. Irwin, "Exploring technology alternatives for nanoscale FPGA interconnects," in Proc. DAC'05, Jun. 2005, pp. 921-926.
15. J. Hone et al., "Electrical and thermal transport properties of magnetically aligned single wall carbon nanotube films," App. Phy. Lett., vol. 77, no. 5, pp. 666-668, 2000.
16. B. Kaustav, L. Sheng-Chih, and S. Navin, "Electrothermal engineering in the nanometer era: From devices and interconnects to Circuits Syst.," in Proc. Asia South Pacific DAC'06, Yokohama, Japan, 2006, pp. 223-230.
17. A. Kawabata et al., "Carbon nanotube vias for future LSI interconnects," in Proc. IEEE Int.. Interconnect Tech. Conf., Jun. 2004, pp. 251-253.
18. F. Li, D. Chen, L. He, and J. Cong, "Architecture evaluation for power-efficient FPGAs," in Proc. ACM/SIGDA Int. Symp. Field Programmable Gate Arrays, Feb. 2003, pp. 175-184.
19. F. Li, Y. Lin, L. He, D. Chen, and J. Cong, "Power modeling and characteristics of field programmable gate arrays," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 24, no. 11, pp. 1712-1724, Nov. 2005.
20. M. Lin, A. El Gamal, Y. C. Lu, and S. Wong, "Performance benefits of monolithically stacked 3-D-FPGA," in Proc. ACM/SIGDA Int. Symp. Field Programmable Gate Arrays, 2006, pp. 113-122.
21. A. Naeemi and J. D. Meindl, "Monolayer metallic nanotube interconnects: Promising candidates for short local interconnects," IEEE Electron Device Lett., vol. 26, pp. 544-546, Aug. 2005.
22. A. Naeemi, R. Sarvari, and J. D. Meindl, "Performance comparison between carbon nanotube and copper interconnects for gigascale integration (GSI)," IEEE Electron Device Lett., vol. 26, pp. 84-86, Feb. 2005.
23. A. Nieuwoodt and Y. Massoud, "Evaluating the impact of resistance in carbon nanotube bundles for VLSI interconnect using diameter-dependent modeling techniques," IEEE Trans. Electron Devices, vol. 53, no. 10, pp. 2460-2466, Oct. 2006.
24. NRAM, Nantero [Online]. Available: http://www.nantero.com/tech.html
25. R. M. P. Rad and M. Tehranipoor, "A new hybrid FPGA with nanoscale clusters and CMOS routing," in Proc. DAC'06, 2006, pp. 727-730.
26. A. Rahman, S. Das, A. P. Chandrakasan, and R. Reif, "Wiring requirement and three-dimensional integration technology for field programmable gate arrays," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 1, pp. 44-54, Jan. 2003.
27. A. Raychowdhury and K. Roy, "Circuit modeling of carbon nanotube interconnects and their performance estimation in VLSI design," in Proc. Int. Workshop on Computational Electronics (IWCE), West Lafayette, IN, Nov. 2004, pp. 122-123.
28. A. Raychowdhury and K. Roy, "Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technology," IEEE Trans. Computer-Aided Des. Integr. Circuits Syst., vol. 25, no. 1, pp. 58-65, Jan. 2006.
29. E. M. Sentovich et al., SIS: A System for Sequential Circuit Synthesis, Dept. of ECE, Univ. California, Berkeley, CA, 1992.
30. G. Snider, P. Kuekes, and R. S. Williams, "CMOS-like logic in defective nanoscale crossbars," Nanotechnology, vol. 15, pp. 881-891, 2004.
31. N. Srivastava, R. V. Joshi, and K. Banerjee, "Carbon nanotube interconnects: Implications for performance, power dissipation and thermal management," in Tech. Dig. IEDM Electron Devices Meeting, 2005, pp. 249-252.
32. D. B. Strukov and K. K. Likharev, "CMOL FPGA: A reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices," Nanotechnology, vol. 16, no. 888-900, 2005.
33. W. Zhang, N. Jha, and L. Shang, "NATURE: A hybrid nanotube/CMOS dynamically reconfigurable architecture," in Proc. DAC'06, 2006, pp. 711-716.
34. L. Zhu, Y. Xiul, D. W. Hess, and C. P. Wong, "Growth of aligned carbon nanotube arrays for electrical interconnect," in Proc. of Electronics Packaging Technology Conference, 2005, pp. 646-651.
35. International Technology Roadmap for Semiconductors ITRS, San Jose, CA, 2005 [Online]. Available: http://www.public.itrs.net
36. "Fujitsu reports progress towards carbon nanotube interconnects for 32 nm," Solid State Technol., Nov. 2006 [Online]. Available: http://sst.pennnet.com/display_article/276187/5/ARTCL/none/FEATA/ -November-2006-Asian-Exclusive-Feature-1:-Fujitsu-reports- progress-towards-carbon-nanotube-interconnects-for-32nm-/
37. G. Snider and S. Williams, "Nano/CMOS architecture using a field-programmable nanowire interconnect," Nanotechnology, vol. 18, no. 3, 2007, to be published.
38. A. Kawabata et al., "Carbon nanotube vias for future LSI interconnects," in Proc. IEEE Int.. Interconnect Tech. Conf., Jun. 2004, pp. 251-253.