Prefetch-aware memory controllers

IEEE Transactions on Computers

Volumn 60, Issue 10, 2011, Pages 1406-1430

  Lee, Chang Joo ^a   Mutlu, Onur ^b   Narasiman, Veynu ^a   Patt, Yale N ^a  

^a The University of Texas at Austin   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

DRAM; memory controllers; Memory systems; multi core systems; prefetching

Indexed keywords

BANDWIDTH CONSUMPTION; BUFFER MANAGEMENT; LOW HARDWARE COSTS; MEMORY CONTROLLER; MEMORY SYSTEMS; MULTI-CORE SYSTEMS; PERFORMANCE LOSS; PREFETCHES; PREFETCHING;

BANDWIDTH; CONTROLLERS; MICROPROCESSOR CHIPS; MULTIPROGRAMMING; SCHEDULING;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 80052580456     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2010.214     Document Type: Article

References (47)

1. J. Baer and T. Chen, "An Effective On-Chip Preloading Scheme to Reduce Data Access Penalty," Proc. ACM/IEEE Conf. Supercomputing (Supercomputing '91), pp. 178-186, 1991.
2. M. Charney and T. Puzak, "Prefetching and Memory System Behavior of the SPEC95 Benchmark Suite," IBM J. Research and Development, vol. 31, no. 3, pp. 265-286, 1997.
3. V. Cuppu, B. Jacob, B. Davis, and T. Mudge, "A Performance Comparison of Contemporary DRAM Architectures," Proc. 26th Ann. Int'l Symp. Computer Architecture (ISCA-26), pp. 222-233, 1999.
4. S. Eyerman and L. Eeckhout, "System-Level Performance Metrics for Multiprogram Workloads," IEEE Micro, vol. 28, no. 3, pp. 42-53, May 2008.
5. J.D. Gindele, "Buffer Block Prefetching Method," IBM Technical Disclosure Bull., vol. 20, no. 2, pp. 696-697, July 1977.
6. G. Hinton, D. Sager, M. Upton, D. Boggs, D. Carmean, A. Kyker, and P. Roussel, "The Microarchitecture of the Pentium 4 Processor," Intel Technology J., vol. 1, p. 2001, Feb. 2001.
7. I. Hur and C. Lin, "Adaptive History-Based Memory Scheduler," Proc. 37th Ann. IEEE/ACM Int'l Symp. Microarchitecture (MICRO-37), 2004.
8. I. Hur and C. Lin, "Memory Prefetching Using Adaptive Stream Detection," Proc. 39th Ann. IEEE/ACM Int'l Symp. Microarchitecture (MICRO-39), 2006.
9. D. Joseph and D. Grunwald, "Prefetching Using Markov Predictors," Proc. 24th Ann. Int'l Symp. Computer Architecture (ISCA-24), pp. 252-263, 1997.
10. R. Kalla, B. Sinharoy, and J.M. Tendler, "IBM Power5 Chip: A Dual-Core Multithreaded Processor," IEEE Micro, vol. 24, no. 2, pp. 40-47, Mar./Apr. 2004.
11. T. Karkhanis and J.E. Smith, "A Day in the Life of a Data Cache Miss," Proc. Second Workshop Memory Performance Issues, 2002.
12. H.Q. Le, W.J. Starke, J.S. Fields, F.P. O'Connell, D.Q. Nguyen, B.J. Ronchetti, W.M. Sauer, E.M. Schwarz, and M.T. Vaden, "IBM Power6 Microarchitecture," IBM J. Research and Development, vol. 51, pp. 639-662, 2007.
13. C.J. Lee, O. Mutlu, V. Narasiman, and Y.N. Patt, "Prefetch-Aware DRAM Controllers," Proc. 41st Ann. IEEE/ACM Int'l Symp. Microarchitecture (MICRO-41), 2008.
14. W.-F. Lin, S.K. Reinhardt, and D. Burger, "Reducing DRAM Latencies with an Integrated Memory Hierarchy Design," Proc. Seventh Int'l Symp. High-Performance Computer Architecture (HPCA-7), pp. 301-312, 2001.
15. K. Luo, J. Gummaraju, and M. Franklin, "Balancing Throughput and Fairness in SMT Processors," Proc. IEEE Int'l Symp. Performance Analysis of Systems and Software (ISPASS), pp. 164-171, 2001.
16. S. McFarling, "Combining Branch Predictors," Technical Report TN-36, Digital Western Research Laboratory, June 1993.
17. S.A. McKee, W.A. Wulf, J.H. Aylor, R.H. Klenke, M.H. Salinas, S.I. Hong, and D.A. Weikle, "Dynamic Access Ordering for Streamed Computations," IEEE Trans. Computers, vol. 49, no. 11, pp. 1255-1271, Nov. 2000.
18. Micron, 2Gb DDR3 SDRAM, MT41J512M4-64 Meg x 4 x 8 Banks, http://download.micron.com/pdf/datasheets/dram/ddr3/, 2009.
19. T.C. Mowry, M.S. Lam, and A. Gupta, "Design and Evaluation of a Compiler Algorithm for Prefetching," Proc. Fifth Int'l Conf. Architectural Support for Programming Languages and Operating Systems, pp. 62-73, 1992.
20. O. Mutlu, H. Kim, D.N. Armstrong, and Y.N. Patt, "Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References," Int'l J. Parallel Programming, vol. 33, no. 5, pp. 529-559, Oct. 2005.
21. O. Mutlu, H. Kim, and Y.N. Patt, "Techniques for Efficient Processing in Runahead Execution Engines," Proc. Ann. 32nd Int'l Symp. Computer Architecture (ISCA-32), 2005.
22. O. Mutlu and T. Moscibroda, "Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors," Proc. 40th Ann. IEEE/ACM Int'l Symp. Microarchitecture (MICRO-40), 2007.
23. O. Mutlu and T. Moscibroda, "Parallelism-Aware Batch Scheduling: Enhancing Both Performance and Fairness of Shared DRAM Systems," Proc. 35th Ann. Int'l Symp. Computer Architecture (ISCA-35), 2008.
24. O. Mutlu, J. Stark, C. Wilkerson, and Y.N. Patt, "Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors," Proc. Ninth Int'l Symp. High-Performance Computer Architecture (HPCA-9), 2003.
25. C. Natarajan, B. Christenson, and F. Briggs, "A Study of Performance Impact of Memory Controller Features in Multi-Processor Server Environment," Proc. Workshop Memory performance Issues (WMPI), pp. 80-87, 2004.
26. K.J. Nesbit, N. Aggarwal, J. Laudon, and J.E. Smith, "Fair Queuing Memory Systems," Proc. 39th Ann. IEEE/ACM Int'l Symp. Microarchitecture (MICRO-39), 2006.
27. K.J. Nesbit, A.S. Dhodapkar, J. Laudon, and J.E. Smith, "AC/DC: An Adaptive Data Cache Prefetcher," Proc. 13th Int'l Conf. Parallel Architecture and Compilation Techniques (PACT-13), 2004.
28. H. Patil, R. Cohn, M. Charney, R. Kapoor, A. Sun, and A. Karunanidhi, "Pinpointing Representative Portions of Large Intel Itanium Programs with Dynamic Instrumentation," Proc. 37th Ann. IEEE/ACM Int'l Symp. Microarchitecture (MICRO-37), 2004.
29. M.K. Qureshi, D.N. Lynch, O. Mutlu, and Y.N. Patt, "A Case for MLP-Aware Cache Replacement," Proc. 33rd Ann. Int'l Symp. Computer Architecture (ISCA-33), 2006.
30. S. Rixner, "Memory Controller Optimizations for Web Servers," Proc. 37th Ann. IEEE/ACM Int'l Symp. Microarchitecture (MICRO-37), 2004.
31. S. Rixner, W.J. Dally, U.J. Kapasi, P. Mattson, and J.D. Owens, "Memory Access Scheduling," Proc. 27th Ann. Int'l Symp. Computer Architecture (ISCA-27), 2000.
32. A.J. Smith, "Cache Memories," Computing Surveys, vol. 14, no. 4, pp. 473-530, 1982.
33. W.E. Smith, "Various Optimizers for Single Stage Production," Naval Research Logistics Quarterly, vol. 3, pp. 59-66, 1956.
34. A. Snavely and D.M. Tullsen, "Symbiotic Job Scheduling for a Simultaneous Multithreading Processor," Proc. Ninth Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS-9), pp. 164-171, 2000.
35. L. Spracklen and S.G. Abraham, "Chip Multithreading: Opportunities and Challenges," Proc. 11th Int'l Symp. High-Performance Computer Architecture (HPCA-11), pp. 248-252, 2005.
36. S. Srinath, O. Mutlu, H. Kim, and Y.N. Patt, "Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers," Proc. 13th Int'l Symp. High-Performance Computer Architecture (HPCA-13), 2007.
37. V. Srinivasan, G.S. Tyson, and E.S. Davidson, "A Static Filter for Reducing Prefetch Traffic," Technical Report CSE-TR-400-99, Univ. of Michigan, 1999.
38. Sun Microsystems, Inc., OpenSPARC T1 Microarchitecture Specification.
39. J. Tendler, S. Dodson, S. Fields, H. Le, and B. Sinharoy, "POWER4 System Microarchitecture," IBM Technical White Paper, Oct. 2001.
40. O. Wechsler, "Inside Intel Core Microarchitecture," Intel Technical White Paper, 2006.
41. T.-Y. Yeh and Y.N. Patt, "Alternative Implementations of Two-Level Adaptive Branch Prediction," Proc. 19th Ann. Int'l Symp. Computer Architecture (ISCA-19), 1992.
42. C. Zhang and S.A. McKee, "Hardware-Only Stream Prefetching and Dynamic Access Ordering," Proc. 14th Int'l Conf. Supercomputing (ICS-14), 2000.
43. Z. Zhang, Z. Zhu, and X. Zhang, "A Permutation-Based Page Interleaving Scheme to Reduce Row-Buffer Conflicts and Exploit Data Locality," Proc. 27th Ann. Int'l Symp. Computer Architecture (ISCA-27), 2000.
44. Z. Zhu and Z. Zhang, "A Performance Comparison of DRAM Memory System Optimizations for SMT Processors," Proc. 11th Int'l Symp. High-Performance Computer Architecture (HPCA-11), 2005.
45. X. Zhuang and H.-H.S. Lee, "A Hardware-Based Cache Pollution Filtering Mechanism for Aggressive Prefetches," Proc. 32nd Int'l Conf. Parallel Processing, pp. 286-293, 2003.
46. X. Zhuang and H.-H.S. Lee, "Reducing Cache Pollution via Dynamic Data Prefetch Filtering," IEEE Trans. Computers, vol. 56, no. 1, pp. 18-31, Jan. 2007.
47. W. Zuravleff and T. Robinbson, "Controller for a Synchronous DRAM That Maximizes Throughput by Allowing Memory Requests and Commands to be Issued Out of Order," US Patent Number 5,630,096, 1997.