A study of performance impact of memory controller features in multi-processor server environment

ACM International Conference Proceeding Series

Volumn 68, Issue , 2004, Pages 80-87

  Natarajan, Chitra ^a   Christenson, Bruce ^a   Briggs, Fayé ^a  

^a INTEL CORPORATION   (United States)

Author keywords

memory controller; memory subsystem; memory transaction scheduling; multi processors; performance impact; server systems

Indexed keywords

MEMORY CONTROLLER; MEMORY SUBSYSTEMS; MULTI-PROCESSORS; PERFORMANCE IMPACT; SERVER SYSTEM; TRANSACTION SCHEDULING;

COMPUTERS; CONTROLLERS; MULTIPROCESSING SYSTEMS; NANOTECHNOLOGY; OPTIMIZATION; PROGRAM PROCESSORS; SCHEDULING;

COMPUTER ARCHITECTURE;

EID: 77954429175     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1054943.1054954     Document Type: Conference Paper

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