Dynamic access ordering for streamed computations

IEEE Transactions on Computers

Volumn 49, Issue 11, 2000, Pages 1255-1271

  McKee, Sally A ^a,e   Wulf, William A ^b,e   Aylor, James H ^b,e   Klenke, Robert H ^c,e   Salinas, Maximo H ^b,e   Hong, Sung I ^d   Weikle, Dee A B ^b,e  

^a Department of Electrical and Computer Engineering   (United States)

^b University of Virginia   (United States)

^c Virginia Commonwealth University   (United States)

^d LOCKHEED MARTIN   (United States)

^e IEEE

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; CACHE MEMORY; COMPUTER HARDWARE; COMPUTER SIMULATION; MULTIMEDIA SYSTEMS; PROGRAM COMPILERS; RESPONSE TIME (COMPUTER SYSTEMS); STORAGE ALLOCATION (COMPUTER);

DYNAMIC ACCESS STORAGE; MEMORY ACCESS ORDERING; MEMORY ACCESS SCHEDULING; MEMORY LATENCY; MEMORY SYSTEMS ARCHITECTURE; STREAMED COMPUTATIONS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0034314462     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.895941     Document Type: Article

References (53)

1. M.J. Alexander, M.W. Bailey, B.R. Childers, J.W. Davidson, and S. Jinturkar, "Memory Bandwidth Optimizations for Wide-Bus Machines," Proc. IEEE 26th Hawaii Int'l Conf. Systems Sciences (HICSS-26), pp. 466-475, Jan. 1993. (Incorrectly published under M.A. Alexander et al.).
2. J.-L. Baer and T.-F. Chen, "An Effective On-Chip Preloading Scheme to Reduce Data Access Penalty," Proc. Supercomputing '91, pp. 176-186, Nov. 1991.
3. N.J. Boden, D. Cohen, R.E. Felderman, A.E. Kulawik, C.L. Seitz, J.N. Seizovic, and W.-K. Su, "Myrinet - A Gigabit-per-Second Local-Area Network," IEEE Micro, vol. 15, no. 1, pp. 29-36, Feb. 1995.
4. M.E. Benitez and J.W. Davidson, "Code Generation for Streaming: An Access/Execute Mechanism," Proc. Fourth Symp. Architectural Support for Programming Languages and Operating Systems, pp. 132-141, Apr. 1991.
5. D. Burger, J.R. Goodman, and A. Kägi, "The Declining Effectiveness of Dynamic Caching for General-Purpose Microprocessors," Technical Report 1261, Univ. Wisconsin, 1995.
6. J. Brooks, "Single PE Optimization Techniques for the Cray T3D System," Proc. First European T3D Workshop, Sept. 1995.
7. P.L. Bird and R.A. Uhlig, "Using Lookahead to Reduce Memory Bank Contention for Decoupled Operand References," Proc. Supercomputing '91, pp. 187-196, Nov. 1991.
8. W.Y. Chen, R.A. Bringmann, S.A. Mahlke, R.E. Hank, and J.E. Sicolo, "An Efficient Architecture for Loop Based Data Preloading," Proc. IEEE/ACM 25th Int'l Symp. Microarchitecture, pp. 92-101, Dec. 1992.
9. J. Corbal, R. Espasa, and M. Valero, "Command Vector Memory Systems: High Performance at Low Cost," Proc. 1998 Int'l Conf. Parallel Architectures and Compilation Techniques, pp. 68-77, Oct. 1998.
10. T.-C. Chiueh, "Sunder: A Programmable Hardware Prefetch Architecture for Numerical Loops," Proc. Supercomputing '94, pp. 488-497, Nov. 1994.
11. J.B. Carter, W.C. Hsieh, L.B. Stoller, M.R. Swanson, L. Zhang, E.L. Brunvand, A. Davis, C.-C. Kuo, R. Kuramkote, M.A. Parker, L. Schaelicke, and T. Tateyama, "Impulse: Building a Smarter Memory Controller," Proc. Fifth Ann. Symp. High Performance Computer Architecture, pp. 70-79, Jan. 1999.
12. R. Cytron, S. Karlovsky, and K.P. McAuliffe, "Automatic Management of Programmable Caches," Proc. 1988 Int'l Conf. Parallel Processing, pp. 229-238, Aug. 1988.
13. D. Callahan, K. Kennedy, and A. Porterfield, "Software Prefetching," Proc. Fourth Symp. Architectural Support for Programming Languages and Operating Systems, pp. 40-52, Apr. 1991.
14. W.Y. Chen, S.A. Mahlke, and W.W. Hwu, "Tolerating Data Access Latency with Register Preloading," Proc. 1992 Int'l Conf. Supercomputing, pp. 104-113, Sept. 1992.
15. R. Crisp, "Direct Rambus Technology: The New Main Memory Standard," IEEE Micro, vol. 17, no. 6, pp. 18-28, Nov./Dec. 1997.
16. D.R. Cheriton, G.A. Slavenburg, and P.D. Boyle, "Software-Controlled Caches in the VMP Multiprocessor," Proc. 13th Ann. Int'l Symp. Computer Architecture, Dec. 1986.
17. A.M. del Corral and J.M. Llaberia, "Access Order to Avoid Inter-Vector Conflicts in Complex Memory Systems," Proc. Ninth Int'l Parallel Processing Symp., 1995.
18. J.J. Dongarra, J. DuCroz, I. Duff, and S. Hammerling, "A Set of Level 3 Basic Linear Algebra Subprograms," ACM Trans. Math. Software, vol. 16, no. 1, pp. 1-17, Mar. 1990.
19. F. Dahlgren, M. Dubois, and P. Stenstrom, "Sequential Hardware Prefetching in Shared-Memory Multiprocessors," IEEE Trans. Parallel and Distributed Systems, vol. 6, no. 7, pp. 733-746, July 1995.
20. J.W. Davidson and S. Jinturkar, "Memory Access Coalescing: A Technique for Eliminating Redundant Memory Accesses," Proc. SIGPLAN '94 Conf. Programming Language Design and Implementation, pp. 186-195, June 1994.
21. K.I. Farkas, P. Chow, N. Jouppi, and Z. Vranesic, "Memory-System Design Considerations for Dynamically-Scheduled Processors," Proc. 24th Ann. Int'l Symp. Computer Architecture, pp. 133-143, June 1997.
22. J.W.C. Fu and J.H. Patel, "Data Prefetching in Multiprocessor Vector Cache Memories," Proc. 18th Ann. Int'l Symp. Computer Architecture, pp. 54-65, May 1991.
23. Q.S. Gao, "The Chinese Remainder Theorem and the Prime Memory System," Proc. 20th Ann. Int'l Symp. Computer Architecture, pp. 337-340, May 1993.
24. D.T. Harper III and J.R. Jump, "Vector Access Performance in Parallel Memories Using a Skewed Storage Scheme," IEEE Trans. Computers, vol. 36, no. 12, pp. 1,440-1,449, Dec. 1987.
25. S.I. Hong, S.A. McKee, M.H. Salinas, R.H. Klenke, J.H. Aylor, and W.A. Wulf, "Access Order and Effective Bandwidth for Streams on a Direct Rambus Memory," Proc. Fifth Ann. Symp. High Performance Computer Architecture, pp. 80-89, Jan. 1999.
26. Intel Corp., i860 64-bit Microprocessor Programmer's Manual, 1990.
27. N.P. Jouppi, "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully Associative Cache and Prefetch Buffers," Proc. 17th Ann. Int'l Symp. Computer Architecture, pp. 364-373, May 1990.
28. M.J. Kilgard, D. Blythe, and D. Hohn, "System Support for OpenGL Direct Rendering," Proc. Graphics Interface '95, May 1995.
29. R.K. Koeninger, M. Furtney, and M. Walker, "A Shared-Memory MPP from Cray Research," Digital Technical J., vol. 6, no. 2, pp. 8-21, 1994.
30. A.C. Klaiber and H.M. Levy, "An Architecture for Software-Controlled Data Prefeching," Proc. 18th Ann. Int'l Symp. Computer Architecture, pp. 43-53, May 1991.
31. D. Loshin and D. Budge, "Breaking the Memory Bottleneck, Parts 1 & 2," Supercomputing Review, Jan./Feb. 1992.
32. K. Lee, The NAS860 Library User's Manual, NASA Ames Research Center, Mar. 1993.
33. A.M. Mainwaring and D.E. Culler, "Design Challenges of Virtual Networks: Fast, General-Purpose Communication," Proc. 1999 Conf. Principles and Practice of Parallel Programming, pp. 119-130, May 1999.
34. S.A. McKee, "Maximizing Memory Bandwidth for Streamed Computations," PhD thesis, School of Eng. and Applied Science, Univ. of Virginia, May 1995.
35. F.H. McMahon, "The Livermore Fortran Kernels: A Computer Test of the Numerical Performance Range," Technical Report UCRL-53745, Lawrence Livermore Nat'l Laboratory, Dec. 1986.
36. MIPS Technologies, Inc., MIPS R10000 Microprocessor User's Manual, Version 2.0, Dec. 1996.
37. T.C. Mowry, M.S. Lam, and A. Gupta, "Design and Evaluation of a Compiler Algorithm for Prefetching," Proc. Fifth Symp. Architectural Support for Programming Languages and Operating Systems, pp. 62-73, Oct. 1992.
38. B.K. Mathew, S.A. McKee, J.B. Carter, and A. Davis, "Parallel Access Ordering for SDRAM Memories," Proc. Sicth Ann. Symp. High Performance Computer Architecture, pp. 39-48, Jan. 2000.
39. L. Meadows, S. Nakamoto, and V. Schuster, "A Vectorizing Software Pipelining Compiler for LIW and Superscalar Architectures," Proc. RISC '92, pp. 331-343, 1992.
40. S.A. Moyer, "Access Ordering Algorithms and Effective Memory Bandwidth," PhD thesis, School of Eng. and Applied Science, Univ. of Virginia, May 1993.
41. S.A. McKee and W.A. Wulf, "Access Ordering and Memory-Conscious Cache Utilization," Proc. First Ann. Symp. High Performance Computer Architecture, pp. 253-262, Jan. 1995.
42. S. Palacharla and R.E. Kessler, "Evaluating Stream Buffers as a Secondary Cache Replacement," Proc. 21st Ann. Int'l Symp. Computer Architecture, pp. 24-33, May 1994.
43. S. Palacharla and R.E. Kessler, "Code Restructuring to Exploit Page Mode and Read-Ahead Features of the Cray T3D," Cray Research Internal Report, Feb. 1995.
44. Rambus, Inc., "Direct Rambus Technology Overview," 1997. http://www.rambus.com/html/documentation.html.
45. Rambus, Inc., "64M/72M Direct RDRAM Data Sheet,"DL 0035-00.c0.5.28, Mar. 1998. http://www.rambus.com/html/ documentation.html.
46. B.R. Rau, "Pseudo-Randomly Interleaved Memory," Proc. 18th Ann. Int'l Symp. Computer Architecture, pp. 74-83, May 1991.
47. S. Scott, "Synchronization and Communication in the T3E Multiprocessor," Proc. Seventh Symp. Architectural Support for Programming Languages and Operating Systems, pp. 26-36, Oct. 1996.
48. I. Sklenar, "Prefetch Unit for Vector Operation on Scalar Computers," Computer Architecture News, vol. 20, no. 4, pp. 31-37, Sept. 1992.
49. M.R. Swanson, L.B. Stoller, and J.B. Carter, "Increasing TLB Reach Using Superpages Backed by Shadow Memory," Proc. 25th Ann. Int'l Symp. Computer Architecture, pp. 204-213, June 1998.
50. M. Valero, T. Lang, J.M. Llaberia, M. Peiron, E. Ayguade, and J.J. Navarro, "Increasing the Number of Strides for Conflict-Free Vector Access," Proc. 19th Ann. Int'l Symp. Computer Architecture, pp. 372-381, May 1992.
51. M. Valero, T. Lang, M. Peiron, and E. Ayguade, "Conflict-Free Access for Streams in Multi-Module Memories," Technical Report UPC-DAC-93-11, Universitat Politecnica de Catalunya, Barcelona, Spain, 1993.
52. W.A. Wulf and S.A. McKee, "Hitting the Wall: Implications of the Obvious," Computer Architecture News, vol. 23, no. 1, pp. 20-24, Mar. 1995.
53. L. Zhang, J.B. Carter, W.C. Hsieh, and S.A. McKee, "Memory System Support for Image Processing," Proc. 1999 Int'l Conf. Parallel Architectures and Compilation Techniques, pp. 98-107, Oct. 1999.