A performance comparison of DRAM memory system optimizations for SMT processors

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2005, Pages 213-222

  Zhu, Zhichun ^a   Zhang, Zhao ^b  

^a 1120 Science and Engineering Offices   (United States)

^b Iowa State University of Science and Technology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MEMORY CONCURRENCY; MEMORY SYSTEMS; SIMULTANEOUS MULTITHREADING (SMT); SYSTEM OPTIMIZATIONS;

OPTIMIZATION; PROGRAM PROCESSORS; SENSITIVITY ANALYSIS; SOCIETIES AND INSTITUTIONS; STORAGE ALLOCATION (COMPUTER); SURFACE MOUNT TECHNOLOGY;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 28444470842     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2005.2     Document Type: Conference Paper

References (34)

1. L. A. Barroso, K. Gharachorloo, R. McNamara, A. Nowatzyk, S. Qadeer, B. Sano, S. Smith, R. Stets, and B. Verghese. Piranha: a scalable architecture based on single-chip multiprocessing. In Proceedings of the 27th Annual International Symposium on Computer Architecture, pages 282-293, 2000.
2. rd Annual International Symposium on Computer Architecture, pages 78-89, 1996.
3. F. J. Cazorla, E. Fernandez, A. Ramirez, and M. Valero. Dcache warn: an I-Fetch policy to increase SMT efficiency. In Proceedings of the 18th International Parallel and Distributed Processing Symposium, 2004.
4. V. Cuppu and B. Jacob. Concurrency, latency, or system overhead: Which has the largest impact on uniprocessor DRAM-system performance? In Proceedings of the 28th Annual International Symposium on Computer Architecture, pages 62-71, 2001.
5. V. Cuppu, B. Jacob, B. Davis, and T. Mudge. A performance comparison of contemporary DRAM architectures. In Proceedings of the 26th Annual International Symposium on Computer Architecture (ISCA'99), pages 222-233, 1999.
6. R. Desikan, D. Burger, and S. W. Keckler. Measuring experimental error in microprocessor simulation. In Proceedings of the 28th Annual International Symposium on Computer Architecture, pages 266-277, 2001.
7. A. El-Moursy and D. H. Albonesi. Front-end policies for improved issue efficiency in SMT processors. In Proceedings of the Ninth International Symposium on High-Performance Computer Architecture, pages 31-41, 2003.
8. W. fen Lin, S. K. Reinhardt, and D. Burger. Reducing DRAM latencies with an integrated memory hierarchy design. In Proceedings of the Seventh International Symposium on High-Performance Computer Architecure, pages 301-312, 2001.
9. M. Gulati and N. Bagherzadeh. Performance study of a multithreaded superscalar microprocessor. In Proceedings of the 2nd International Symposium on High-Performance Computer Architecture, pages 291-302, 1996.
10. L. Hammond, B. A. Nayfeh, and K. Olukotun. A single-chip multiprocessor. Computer, 30(9):79-85, Sept. 1997.
11. H. Hidaka, Y. Matsuda, M. Asakura, and K. Fujishima. The cache DRAM architecture: a DRAM with an on-chip cache memory. IEEE Micro, 10(2):14-25, Apr. 1990.
12. H. Hirata, K. Kimura, S. Nagamine, Y. Mochizuki, A. Nishimura, Y. Nakase, and T. Nishizawa. An elementary processor architecture with simultaneous instruction issuing from multiple threads. In Proceedings of the 19th Annual International Symposium on Computer Architecture, pages 136-145, Gold Coast, Australia, May 1992.
13. S. I. Hong, S. A. McKee, M. H. Saunas, R. H. Klenke, J. H. Aylor, and W. A. Wulf. Access order and effective bandwidth for streams on a Direct Rambus memory. In Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, pages 80-89, Jan. 1999.
14. J. Lo, L. Barroso, S. Eggers, K. Gharachorloo, H. Levy, and S. Parekh. An analysis of database workload performance on simultaneous multithreaded processors. In Proceedings of the 25th Annual International Symposium on Computer Architecture (ISCA-98), pages 39-51, June 27-July 1 1998.
15. K. Luo, J. Gummaraju, and M. Franklin. Balancing though-put and fairness in SMT processors. In International Symposium on Performance Analysis of Systems and Software, pages 164-171, 2001.
16. B. K. Mathew, S. A. McKee, J. B. Carter, and A. Davis. Design of a parallel vector access unit for SDRAM memory systems. In Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, pages 39-48, Jan. 2000.
17. S. A. McKee and W. A. Wulf. Access ordering and memory-conscious cache utilization. In Proceedings of the First International Symposium on High-Performance Computer Architecture, pages 253-262, Jan. 1995.
18. S.A. Moyer. Access Ordering and Effective Memory Band-width. PhD thesis, University of Virginia, Department of Computer Science, Apr. 1993. Also as TR CS-93-18.
19. V. S. Pai and S. Adve. Code transformations to improve memory parallelism. In Proceedings of the 32nd Annual International Symposium on Microarchitecture, pages 147-155, 1999.
20. J. Redstone, H. Levy, and S. Eggers. An analysis of operating system behavior on a simultaneous multithreaded architecture. In Proceedings of the 9th International Conference on Architectural Support for Programming Language and Operating Systems, pages 245-256, Nov. 2000.
21. S. Rixner, W. J. Daily, U. J. Kapasi, B. Khailany, A. Lopez-Lagunas, P. R. Mattson, and J. D. Owens. A bandwidth-efficient architecture for media processing. In Proceedings of the 31st Annual ACM/IEEE International Symposium on Microarchitecture, pages 3-13, Nov. 1998.
22. S. Rixner, W. J. Dally, U. J. Kapasi, P. Mattson, and J. D. Owens. Memory access scheduling. In Proceedings of the 27th Annual International Symposium on Computer Architecture, pages 128-138, 2000.
23. T. Sherwood, E. Perelman, G. Hamerly, and B. Calder. Automatically characterizing large scale program behavior. In Proceedings of the Tenth International Conference on Architectural Support for Programming Languages and Operating Systems, pages 45-57, 2002.
24. K. Skadron and D. W. Clark. Design issues and tradeoffs for write buffers. In Proceedings of the Third International Symposium on High Performance Computer Architecture (HPCA '97), pages 144-155, Feb. 1997.
25. A. Snavely, D. Tullsen, and G. Voelker. Symbiotic job-scheduling with priorities for a simultaneous multithreading processor. In Proceedings of the 2002 International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS-02), pages 66-76, June 2002.
26. Standard Performance Evaluation Corporation. SPEC CPU2000. http://www.spec.org.
27. N. Tuck and D. M. Tullsen. Initial observations of the simultaneous multithreading Pentium 4 processor. In Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques, pages 26-35, 2003.
28. D. M. Tullsen and J. A. Brown. Handling long-latency loads in a simultaneous multithreading processor. In Proceedings of the 34th Annual International Symposium on Microarchitecture, pages 318-327, Austin, Texas, Dec. 2001.
29. D. M. Tullsen, S. J. Eggers, J. S. Emer, H. M. Levy, J. L. Lo, and R. L. Stamm. Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor. In Proceedings of the 23rd Annual International Symposium on Computer Architecture, pages 191-202, 1996.
30. D. M. Tullsen, S. J. Eggers, and H. M. Levy. Simultaneous multithreading: Maximizing on-chip parallelism. In P roc. of the 22nd Annual International Symposium on Computer Architecture, pages 392-403, 1995.
31. D. M. Tullsen, J. L. Lo, S. J. Eggers, and H. M. Levy. Supporting fine-grained synchronization on a simultaneous multithreading processor. In Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, pages 54-58, Jan. 1999.
32. W. Wong and J.-L. Baer. DRAM on-chip caching. Technical Report UW CSE 97-03-04, University of Washington, Feb. 1997.
33. Z. Zhang, Z. Zhu, and X. Zhang. A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality. In Proceedings of the 33rd Annual International Symposium on Microarchitecture, pages 32-41, 2000.
34. Z. Zhu, Z. Zhang, and X. Zhang. Fine-grain priority scheduling on multi-channel memory systems. In Proceedings the Eighth International Symposium on High-Performance Computer Architecture, pages 107-116, 2002.