A hardware-based cache pollution filtering mechanism for aggressive prefetches

Proceedings of the International Conference on Parallel Processing

Volumn 2003-January, Issue , 2003, Pages 286-293

  Zhuang, X ^a   Lee, H H S ^b  

^a Georgia Institute of Technology   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Bandwidth; Bridges; Degradation; Delay; Filtering; Filters; Hardware; Pollution; Prefetching; Process design

Indexed keywords

ALGORITHMS; BANDWIDTH; BRIDGES; BUFFER STORAGE; COMPUTER HARDWARE; DEGRADATION; FILTERS (FOR FLUIDS); FILTRATION; HARDWARE; MEMORY ARCHITECTURE; PARALLEL PROCESSING SYSTEMS; POLLUTION; POLLUTION CONTROL; PROCESS DESIGN;

DELAY; FILTERING MECHANISM; HARDWARE AND SOFTWARE; MEMORY ACCESS LATENCY; MEMORY BANDWIDTHS; PERFORMANCE DEGRADATION; PREFETCH ALGORITHMS; PREFETCHING;

CACHE MEMORY;

EID: 84944748972     PISSN: 01903918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPP.2003.1240591     Document Type: Conference Paper

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