Power-gated arithmetic circuits for energy-precision tradeoffs In mobile Graphics Processing Units

Journal of Low Power Electronics

Volumn 7, Issue 2, 2011, Pages 148-162

  Pool, Jeff ^a   Lastra, Anselmo ^a   Singh, Montek ^a  

^a University of North Carolina   (United States)

Author keywords

Arithmetic circuits; Graphics hardware; Low power; Variable precision

Indexed keywords

COMPUTER GRAPHICS; COMPUTER GRAPHICS EQUIPMENT; ENERGY EFFICIENCY; ENERGY UTILIZATION; IMAGE CODING; LOGIC CIRCUITS; LOW POWER ELECTRONICS; PIPELINE PROCESSING SYSTEMS; PIPELINES; PROGRAM PROCESSORS; SPICE; TIMING CIRCUITS;

ARITHMETIC CIRCUIT; CIRCUIT LEVEL DESIGN; FINE-GRAINED POWER GATING; GRAPHICS HARDWARE; GRAPHICS PROCESSOR; LOW POWER; SPICE SIMULATIONS; VARIABLE PRECISION;

GRAPHICS PROCESSING UNIT;

EID: 80052442953     PISSN: 15461998     EISSN: 15462005     Source Type: Journal    
DOI: 10.1166/jolpe.2011.1124     Document Type: Article

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