Design and implementation of fine-grain power gating with ground bounce suppression

Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems

Volumn , Issue , 2009, Pages 381-386

  Usami, Kimiyoshi ^a   Shirai, Toshiaki ^a   Hashida, Tasunori ^a   Masuda, Hiroki ^a   Takeda, Seidai ^c   Nakata, Mitsutaka ^a   Seki, Naomi ^b   Amano, Hideharu ^b   Namiki, Mitaro ^d   Imai, Masashi ^c   Kondo, Masaaki ^e   Nakamura, Hiroshi ^c  

^a SHIBAURA INSTITUTE OF TECHNOLOGY   (Japan)

^b KEIO UNIVERSITY   (Japan)

^c UNIVERSITY OF TOKYO   (Japan)

^d TOKYO UNIVERSITY OF AGRICULTURE AND TECHNOLOGY   (Japan)

^e UNIVERSITY OF ELECTRO COMMUNICATIONS   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

90NM CMOS; ACTIVE STATE; BENCHMARK PROGRAMS; BREAK-EVEN POINTS; CPU CORES; DRIVING POWER; EXECUTION TIME; FINE GRANULARITIES; FUNCTION UNITS; GROUND BOUNCES; IDLE TIME; IMPLEMENTATION METHODOLOGIES; INTERNAL FUNCTIONS; NOVEL TECHNIQUES; POWER DOMAINS; POWER GATING; POWER SAVINGS; POWER SWITCHES; RUN-TIME; SIMULATION RESULTS; TEMPERATURE DEPENDENTS; TOTAL POWER DISSIPATIONS; TRANSITION TIME;

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; DESIGN; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUITS; PLASMA WAVES; POLARIZATION;

EMBEDDED SYSTEMS;

EID: 62949189195     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSI.Design.2009.63     Document Type: Conference Paper

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