High-performance low-power left-to-right array multiplier design

IEEE Transactions on Computers

Volumn 54, Issue 3, 2005, Pages 272-283

  Huang, Zhijun ^a   Ercegovac, Miloš D ^b  

^a MAGMA DESIGN AUTOMATION   (United States)

^b Engineering IV   (United States)

Author keywords

High performance design; Layout regularity; Left to right array multiplier; Low power design; Tree multiplier

Indexed keywords

ADDERS; ALGORITHMS; COMPUTATIONAL COMPLEXITY; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; LOGIC GATES; OPTIMIZATION; VLSI CIRCUITS;

HIGH PERFORMANCE DESIGN; LAYOUT REGULARITY; LEFT-TO-RIGHT ARRAY MULTIPLIER; LOW POWER DESIGN; TREE MULTIPLIER;

MULTIPLYING CIRCUITS;

EID: 14844364761     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2005.51     Document Type: Article

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