Sleep transistor design and implementation - Simple concepts yet challenges to be optimum

2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

Volumn , Issue , 2007, Pages 51-54

  Kaijian, Shi ^a   Howard, David ^b  

^a SYNOPSYS INC   (United States)

^b ARM LTD   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

LEAKAGE CURRENTS; OPTIMIZATION;

POWER-GATING DESIGN; SLEEP TRANSISTOR DESIGN;

TRANSISTORS;

EID: 34748857967     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VDAT.2006.258121     Document Type: Conference Paper

References (6)

1. Kaushik Roy, Saibal Mukhopadhyay, and Hamid Mahmoodi-meimand, "Leakage current mechanism and leakage reduction techniques in deep-designing submicrometer CMOS circuits", Proc. IEEE Vol. 91, no. 2, Feb. 2003
2. Dongwoo Lee, David Blaauw, and Dennis Sylvester, "Gate oxide leakage current analysis and reduction for VLSI circuits", - IEEE Trans. VLSI, Vol.12, No.2, Feb. 2004
3. M. Powell,S.-H Yang, et. al."Gated-Vdd: A circuit technique to reduce leakage in deep-submicron cache memories," in Proc. Int. Symp. Low Power Electronics Design, 2002, pp. 90-95.
4. Satoshi Shigematsu et. al., "A 1-V high-speed MTCMOS circuit scheme for power-down application circuits", IEEE J. Solid-State Circuits, vol. 32, no. 6, June, 1997
5. Benton H Calhoun, Frank A Honore and Anantha P Chandrakasan, "A leakage reduction methodology for distributed MTCMOS", IEEE J. Solid-State Circuits, vol. 39, no. 5, May, 2004, pp. 818-826
6. Changbo Long and Lei He, "Distributed sleep transistor network for power reduction", Proc. IEEE/ACM Design Automation Conference, 2003