메뉴 건너뛰기




Volumn , Issue , 2004, Pages 343-348

Data wordlength reduction for low-power signal processing software

Author keywords

[No Author keywords available]

Indexed keywords

LINEAR FILTERS; SIGNAL PROCESSING SOFTWARE; SWITCHING ACTIVITY; WORDLENGTH REDUCTION;

EID: 17044394759     PISSN: 15206130     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIPS.2005.1579890     Document Type: Conference Paper
Times cited : (15)

References (11)
  • 1
    • 0029293575 scopus 로고
    • Minimizing power consumption in digital CMOS circuits
    • A. P. Chandrakasan and R. W. Brodersen, "Minimizing power consumption in digital CMOS circuits," Proceedings of the IEEE, vol. 83, pp. 498-523, 1995.
    • (1995) Proceedings of the IEEE , vol.83 , pp. 498-523
    • Chandrakasan, A.P.1    Brodersen, R.W.2
  • 2
    • 0042420597 scopus 로고    scopus 로고
    • Minimization of switching activities of partial products for designing low-power multipliers
    • Oscal T.-C. Chen, Sandy Wang, and Yi-Wen Wu, "Minimization of switching activities of partial products for designing low-power multipliers," IEEE Transactions on VLSI Systems, vol. 11, pp. 418-433, 2003.
    • (2003) IEEE Transactions on VLSI Systems , vol.11 , pp. 418-433
    • Chen, O.T.-C.1    Wang, S.2    Wu, Y.-W.3
  • 3
    • 0028711545 scopus 로고
    • Power analysis of embedded software: A first step towards software power minimization
    • San Jose, CA, Nov.
    • V. Tiwari, S. Malik, and A. Wolfe, "Power analysis of embedded software: A first step towards software power minimization," in Proc. IEEE Int. Conf. on Computer-Aided Design, San Jose, CA, Nov. 1994, pp. 429-435.
    • (1994) Proc. IEEE Int. Conf. on Computer-aided Design , pp. 429-435
    • Tiwari, V.1    Malik, S.2    Wolfe, A.3
  • 4
    • 0031099006 scopus 로고    scopus 로고
    • Power analysis and minimization techniques for embedded DSP software
    • M. T. Lee, V. Tiwari, S. Malik, and M. Fujita, "Power analysis and minimization techniques for embedded DSP software," IEEE Transactions on VLSI Systems, vol. 5, pp. 123-135, 1997.
    • (1997) IEEE Transactions on VLSI Systems , vol.5 , pp. 123-135
    • Lee, M.T.1    Tiwari, V.2    Malik, S.3    Fujita, M.4
  • 5
    • 0001146101 scopus 로고
    • A signed binary multiplication technique
    • A.D. Booth, "A signed binary multiplication technique," Quart. J. Mech. Appl. Math., vol. 4, pp. 236-240, 1951.
    • (1951) Quart. J. Mech. Appl. Math. , vol.4 , pp. 236-240
    • Booth, A.D.1
  • 7
    • 0028737371 scopus 로고
    • Search-based wordlength optimization for VLSI/DSP synthesis
    • Oct.
    • H. Choi and W. P. Burleson, "Search-based wordlength optimization for VLSI/DSP synthesis," in Proc. IEEE Workshop on VLSI Signal Processing, Oct. 1994, vol. 7, pp. 198-207.
    • (1994) Proc. IEEE Workshop on VLSI Signal Processing , vol.7 , pp. 198-207
    • Choi, H.1    Burleson, W.P.2
  • 8
    • 0030262410 scopus 로고    scopus 로고
    • Low power multiplication scheme for FIR filter implementation on single multiplier CMOS DSP processors
    • A. T. Erdogan and T. Arslan, "Low power multiplication scheme for FIR filter implementation on single multiplier CMOS DSP processors," IEE Electronics Letters, vol. 32, pp. 1959-1960, 1996.
    • (1996) IEE Electronics Letters , vol.32 , pp. 1959-1960
    • Erdogan, A.T.1    Arslan, T.2
  • 10
    • 84961960473 scopus 로고    scopus 로고
    • Reconfigurable low-energy multiplier for multimedia system design
    • Apr.
    • S. Kim and M. Papaefthymiou, "Reconfigurable low-energy multiplier for multimedia system design," in Proc. IEEE Workshop on VLSI, Apr. 2000, pp. 129-134.
    • (2000) Proc. IEEE Workshop on VLSI , pp. 129-134
    • Kim, S.1    Papaefthymiou, M.2
  • 11
    • 84937739956 scopus 로고
    • A suggestion for a fast multiplier
    • C. S. Wallace, "A suggestion for a fast multiplier," IEEE Transactions on Computers, vol. 13, pp. 14-17, 1964.
    • (1964) IEEE Transactions on Computers , vol.13 , pp. 14-17
    • Wallace, C.S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.