-
1
-
-
33846118079
-
Designing reliable systems from unreliable components: The challenges of transistor variability and degradation
-
DOI 10.1109/MM.2005.110
-
S. Borkar, "Designing reliable systems from unreliable components: The challenges of transistor variability and degradation, " IEEE Micro., vol. 25, no. 6, pp. 10-16, Nov.-Dec. 2005. (Pubitemid 46567817)
-
(2005)
IEEE Micro
, vol.25
, Issue.6
, pp. 10-16
-
-
Borkar, S.1
-
2
-
-
0030387118
-
Gate oxide scaling limits and projection
-
C. Hu, "Gate oxide scaling limits and projection, " in Proc. IEDM, 1996, pp. 319-322.
-
(1996)
Proc. IEDM
, pp. 319-322
-
-
Hu, C.1
-
3
-
-
0036923374
-
Observation of hot-carrier-induced nFET gate-oxide breakdown in dynamically stressed CMOS circuits
-
B. Kaczer, F. Crupi, R. Degraeve, P. Roussel, C. Ciofi, and G. Groeseneker, "Observation of hot-carrier-induced nFET gate-oxide breakdown in dynamically stressed CMOS circuits, " in Proc. IEDM, 2002, pp. 171-174.
-
(2002)
Proc. IEDM
, pp. 171-174
-
-
Kaczer, B.1
Crupi, F.2
Degraeve, R.3
Roussel, P.4
Ciofi, C.5
Groeseneker, G.6
-
4
-
-
34250742624
-
Prediction of logic product failure due to thin-gate oxide breakdown
-
DOI 10.1109/RELPHY.2006.251187, 4017128, 2006 IEEE International Reliability Physics Symposium Proceedings, 44th Annual
-
Y. Lee, N. Mielke, M. Agostinelli, S. Gupta, R. Lu, and W. McMahon, "Prediction of logic product failure due to thin-gate oxide breakdown, " in Proc. IRPS, 2006, pp. 18-28. (Pubitemid 46964486)
-
(2006)
IEEE International Reliability Physics Symposium Proceedings
, pp. 18-28
-
-
Lee, Y.-H.1
Mielke, N.2
Agostinelli, M.3
Gupta, S.4
Lu, R.5
McMahon, W.6
-
5
-
-
0035362378
-
New physics-based analytic approach to the thin-oxide breakdown statistics
-
DOI 10.1109/55.924847, PII S0741310601046729
-
J. Sune, "New physics-based analytic approach to the thin-oxide breakdown statistics, " IEEE Electron Device Lett., vol. 22, no. 6, pp. 296-298, Jun. 2001. (Pubitemid 32585000)
-
(2001)
IEEE Electron Device Letters
, vol.22
, Issue.6
, pp. 296-298
-
-
Sune, J.1
-
6
-
-
0029514106
-
A consistent model for the thickness dependence of intrinsic breakdown in ultra-thin oxides
-
R. Degraeve, G. Groeseneken, R. Bellens, M. Depas, and H. Maes, "A consistent model for the thickness dependence of intrinsic breakdown in ultra-thin oxides, " in Proc. IEDM, 1995, pp. 863-866.
-
(1995)
Proc. IEDM
, pp. 863-866
-
-
Degraeve, R.1
Groeseneken, G.2
Bellens, R.3
Depas, M.4
Maes, H.5
-
7
-
-
0034217271
-
Interrelationship of voltage and temperature dependence of oxide breakdown for ultrathin oxides
-
DOI 10.1109/55.847381
-
E. Wu, D. Harmon, and L. Han, "Interrelationship of voltage and temperature dependence of oxide breakdown for ultrathin oxides, " IEEE Electron Device Lett., vol. 21, no. 7, pp. 362-364, Jul. 2000. (Pubitemid 32075948)
-
(2000)
IEEE Electron Device Letters
, vol.21
, Issue.7
, pp. 362-364
-
-
Wu, E.Y.1
Harmon, D.L.2
Han, L.-K.3
-
8
-
-
0035498572
-
Interplay of voltage and temperature acceleration of oxide breakdown for ultra-thin oxides
-
DOI 10.1016/S0167-9317(01)00629-3, PII S0167931701006293
-
E. Wu, J. Sune, W. Lai, E. Nowak, J. McKenna, A. Vayshenkerb, and D. Harmon, "Interplay of voltage and temperature acceleration of oxide breakdown for ultra-thin gate oxides, " Microelectron. Eng., vol. 59, nos. 1-4, pp. 25-31, 2001. (Pubitemid 33018392)
-
(2001)
Microelectronic Engineering
, vol.59
, Issue.1-4
, pp. 25-31
-
-
Wu, E.1
Sune, J.2
Lai, W.3
Nowak, E.4
McKenna, J.5
Vayshenker, A.6
Harmon, D.7
-
9
-
-
0033280127
-
Temperature acceleration of oxide breakdown and its impact on ultra-thin gate oxide reliability
-
R. Degraeve, N. Pangon, B. Kaczer, T. Nigam, G. Groeseneken, and A. Naem, "Temperature acceleration of oxide breakdown and its impact on ultra-thin gate oxide reliability, " in Proc. VLSIT, 1999, pp. 59-60. (Pubitemid 32214141)
-
(1999)
Digest of Technical Papers - Symposium on VLSI Technology
, pp. 59-60
-
-
Degraeve, R.1
Pangon, N.2
Kaczer, B.3
Nigam, T.4
Groeseneken, G.5
Naem, A.6
-
10
-
-
33646922758
-
Hotspot: Techniques for modeling thermal effects at the processor-architecture level
-
K. Skadron, M. Stan, M. Barcella, A. Dwarka, W. Huang, Y. Li, Y. Ma, A. Naidu, D. Parikh, P. Re, G. Rose, K. Sankaranarayanan, R. Suryanarayan, S. Velusamy, H. Zhang, and Y. Zhang, "Hotspot: Techniques for modeling thermal effects at the processor-architecture level, " in Proc. THERMINICS, 2002, pp. 169-172.
-
(2002)
Proc. THERMINICS
, pp. 169-172
-
-
Skadron, K.1
Stan, M.2
Barcella, M.3
Dwarka, A.4
Huang, W.5
Li, Y.6
Ma, Y.7
Naidu, A.8
Parikh, D.9
Re, P.10
Rose, G.11
Sankaranarayanan, K.12
Suryanarayan, R.13
Velusamy, S.14
Zhang, H.15
Zhang, Y.16
-
11
-
-
79953326313
-
Emulation-based transient thermal modeling of 2D/3D systems-on-chip with active cooling
-
Apr
-
P. D. Valle and D. Atienza, "Emulation-based transient thermal modeling of 2D/3D systems-on-chip with active cooling, " Microelectron. J., vol. 42, no. 4, pp. 564-571, Apr. 2011.
-
(2011)
Microelectron. J.
, vol.42
, Issue.4
, pp. 564-571
-
-
Valle, P.D.1
Atienza, D.2
-
12
-
-
80052062442
-
Thermal modeling and active cooling for 3D MPSoCs
-
Savannah, GA, Aug
-
D. Atienza, "Thermal modeling and active cooling for 3D MPSoCs, " presented at the Lecture MPSoC Forum, Savannah, GA, Aug. 2009.
-
(2009)
The Lecture MPSoC Forum
-
-
Atienza, D.1
-
13
-
-
34548817261
-
Design of the Power6 microprocessor
-
J. Friedrich, B. McCredie, N. James, B. Huott, B. Curran, E. Fluhr, G. Mittal, E. Chan, Y. Chan, D. Plass, S. Chu, H. Le, L. Clark, J. Ripley, S. Taylor, J. Dilullo, and M. Lanzerotti, " Design of the Power6 microprocessor, " in Proc. ISSCC, 2007, pp. 96-97.
-
(2007)
Proc. ISSCC
, pp. 96-97
-
-
Friedrich, J.1
McCredie, B.2
James, N.3
Huott, B.4
Curran, B.5
Fluhr, E.6
Mittal, G.7
Chan, E.8
Chan, Y.9
Plass, D.10
Chu, S.11
Le, H.12
Clark, L.13
Ripley, J.14
Taylor, S.15
Dilullo, J.16
Lanzerotti, M.17
-
14
-
-
49749107911
-
Analysis of system-level reliability factors and implications on real-time monitoring methods for oxide breakdown device failures
-
E. Karl, D. Sylvester, and D. Blaauw, "Analysis of system-level reliability factors and implications on real-time monitoring methods for oxide breakdown device failures, " in Proc. ISQED, 2008, pp. 391-395.
-
(2008)
Proc. ISQED
, pp. 391-395
-
-
Karl, E.1
Sylvester, D.2
Blaauw, D.3
-
15
-
-
0038684860
-
Temperature-aware microarchitecture
-
K. Skadron, M. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan, "Temperature-aware microarchitecture, " in Proc. ISCA, 2003, pp. 2-13.
-
(2003)
Proc. ISCA
, pp. 2-13
-
-
Skadron, K.1
Stan, M.2
Huang, W.3
Velusamy, S.4
Sankaranarayanan, K.5
Tarjan, D.6
-
16
-
-
57849125876
-
A statistical approach for full-chip gate-oxide reliability analysis
-
K. Chopra, C. Zhuo, D. Blaauw, and D. Sylvester, "A statistical approach for full-chip gate-oxide reliability analysis, " in Proc. ICCAD, 2008, pp. 698-705.
-
(2008)
Proc. ICCAD
, pp. 698-705
-
-
Chopra, K.1
Zhuo, C.2
Blaauw, D.3
Sylvester, D.4
-
17
-
-
77953104217
-
Process variation and temperature-aware reliability management
-
C. Zhuo, D. Sylvester, and D. Blaauw, "Process variation and temperature-aware reliability management, " in Proc. DATE, 2010, pp. 580-585.
-
(2010)
Proc. DATE
, pp. 580-585
-
-
Zhuo, C.1
Sylvester, D.2
Blaauw, D.3
-
18
-
-
0346778721
-
Statistical timing analysis considering spatial correlations using a single pert-like traversal
-
H. Chang and S. Sapatnekar, "Statistical timing analysis considering spatial correlations using a single pert-like traversal, " in Proc. ICCAD, 2003, pp. 621-625.
-
(2003)
Proc. ICCAD
, pp. 621-625
-
-
Chang, H.1
Sapatnekar, S.2
-
19
-
-
4444233012
-
First-order incremental block-based statistical timing analysis
-
C. Visweswariah, K. Ravindran, K. Kalafala, S. Walker, and S. Narayan, "First-order incremental block-based statistical timing analysis, " in Proc. DAC, 2004, pp. 331-336.
-
(2004)
Proc. DAC
, pp. 331-336
-
-
Visweswariah, C.1
Ravindran, K.2
Kalafala, K.3
Walker, S.4
Narayan, S.5
-
20
-
-
33745945256
-
Robust extraction of spatial correlation
-
Proceedings of ISPD'06 - 2006 International Symposium on Physical Design
-
J. Xiong, V. Zolotov, and L. He, "Robust extraction of spatial correlation, " in Proc. ISPD, 2006, pp. 2-9. (Pubitemid 44059886)
-
(2006)
Proceedings of the International Symposium on Physical Design
, vol.2006
, pp. 2-9
-
-
Xiong, J.1
Zolotov, V.2
He, L.3
-
21
-
-
70449359316
-
Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability
-
L. Cheng, P. Gupta, C. Spanos, K. Qian, and L. He, "Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability, " in Proc. DAC, 2009, pp. 104-109.
-
(2009)
Proc. DAC
, pp. 104-109
-
-
Cheng, L.1
Gupta, P.2
Spanos, C.3
Qian, K.4
He, L.5
-
22
-
-
43249103476
-
A comprehensive model of process variability for statistical timing optimization
-
K. Qian and C. J. Spanos, "A comprehensive model of process variability for statistical timing optimization, " Proc. SPIE, vol. 6925, pp. 1-11, 2008.
-
(2008)
Proc. SPIE
, vol.6925
, pp. 1-11
-
-
Qian, K.1
Spanos, C.J.2
-
23
-
-
78650889089
-
Active learning framework for post-silicon variation extraction and test cost reduction
-
C. Zhuo, K. Agarwal, D. Sylvester, and D. Blaauw, "Active learning framework for post-silicon variation extraction and test cost reduction, " in Proc. ICCAD, 2010, pp. 508-515.
-
(2010)
Proc. ICCAD
, pp. 508-515
-
-
Zhuo, C.1
Agarwal, K.2
Sylvester, D.3
Blaauw, D.4
-
24
-
-
84954410406
-
Statistical delay computation considering spatial correlations
-
A. Agarwal, D. Blaauw, V. Zolotov, S. Sundareswaran, M. Zhou, K. Gala, and R. Panda, "Statistical delay computation considering spatial correlations, " in Proc. ASPDAC, 2003, pp. 271-276.
-
(2003)
Proc. ASPDAC
, pp. 271-276
-
-
Agarwal, A.1
Blaauw, D.2
Zolotov, V.3
Sundareswaran, S.4
Zhou, M.5
Gala, K.6
Panda, R.7
-
25
-
-
21644481983
-
Implant damage and gate-oxide-edge effects on product reliability
-
Technical Digest - IEEE International Electron Devices Meeting, 2004 IEDM (50th Annual Meeting)
-
Y. Lee, R. Nachman, S. Hu, N. Mielke, and J. Liu, "Implant damage and gate-oxide-edge effects on product reliability, " in Proc. IEDM, 2004, pp. 481-484. (Pubitemid 40928333)
-
(2004)
Technical Digest - International Electron Devices Meeting, IEDM
, pp. 481-484
-
-
Lee, Y.-H.1
Nachman, R.2
Hu, S.3
Mielke, N.4
Liu, J.5
-
26
-
-
36549090991
-
A model for silicon-oxide breakdown under high field and current stress
-
Jun
-
E. Avni and J. Shappir, "A model for silicon-oxide breakdown under high field and current stress, " J. Appl. Phys., vol. 64, pp. 734-742, Jun. 1988.
-
(1988)
J. Appl. Phys.
, vol.64
, pp. 734-742
-
-
Avni, E.1
Shappir, J.2
-
27
-
-
0038529280
-
Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits
-
PII S1530438801042524
-
J. Stathis, "Physical and predictive models of ultra thin oxide reliability in CMOS devices and circuits, " IEEE Trans. Devices Mater. Reliab., vol. 1, no. 1, pp. 43-59, Mar. 2001. (Pubitemid 33778196)
-
(2001)
IEEE Transactions on Device and Materials Reliability
, vol.1
, Issue.1
, pp. 43-59
-
-
Stathis, J.H.1
-
28
-
-
0038443506
-
Statistics of successive breakdown events in gate oxides
-
Apr
-
J. Sune and E. Y. Wu, "Statistics of successive breakdown events in gate oxides, " IEEE Electron Device Lett., vol. 24, no. 4, pp. 272-274, Apr. 2003.
-
(2003)
IEEE Electron Device Lett.
, vol.24
, Issue.4
, pp. 272-274
-
-
Sune, J.1
Wu, E.Y.2
-
29
-
-
0036494245
-
Impact of MOSFET gate oxide breakdown on digital circuit operation and reliability
-
DOI 10.1109/16.987122, PII S0018938302021202
-
B. Kaczer, R. Degraeve, M. Rasras, K. Mieroop, P. Roussel, and G. Groeseneken, "Impact of MOSFET gate oxide breakdown on digital circuit operation and reliability, " IEEE Trans. Electron. Devices, vol. 49, no. 3, pp. 500-506, Mar. 2002. (Pubitemid 34404849)
-
(2002)
IEEE Transactions on Electron Devices
, vol.49
, Issue.3
, pp. 500-506
-
-
Kaczer, B.1
Degraeve, R.2
Rasras, M.3
Van De Mieroop, K.4
Roussel, P.J.5
Groeseneken, G.6
-
30
-
-
77952596529
-
Scalable methods for the analysis and optimization of gate oxide breakdown
-
J. Fang and S. Sapatnekar, "Scalable methods for the analysis and optimization of gate oxide breakdown, " in Proc. ISQED, 2010, pp. 638-645.
-
(2010)
Proc. ISQED
, pp. 638-645
-
-
Fang, J.1
Sapatnekar, S.2
-
31
-
-
0019609684
-
Non-uniformities in ultrathin oxide layers and their effect on the properties of tunnel MOS, MOM, and SOS devices
-
P. Bhatnagar, S. Dhariwal, and G. Srivastava, "Non-uniformities in ultrathin oxide layers and their effect on the properties of tunnel MOS, MOM, and SOS devices, " Physica Status Solidi (A), vol. 67, no. 1, pp. 305-311, 1981. (Pubitemid 12444551)
-
(1981)
Physica Status Solidi (A) Applied Research
, vol.67
, Issue.1
, pp. 305-311
-
-
Bhatnagar, P.K.1
Dhariwal, S.R.2
Srivastava, G.P.3
-
32
-
-
0001507590
-
Computing the distribution of quadratic forms in normal variables
-
J. P. Imhof, "Computing the distribution of quadratic forms in normal variables, " Biometrika, vol. 48, nos. 3-4, pp. 419-426, 1961.
-
(1961)
Biometrika
, vol.48
, Issue.3-4
, pp. 419-426
-
-
Imhof, J.P.1
-
33
-
-
77951255112
-
Two simple approximations to the distributions of quadratic forms
-
K.-H. Yuan and P. M. Bentler, "Two simple approximations to the distributions of quadratic forms, " British J. Math. Statist. Psychol., vol. 63, no. 2, pp. 273-291, 2010.
-
(2010)
British J. Math. Statist. Psychol.
, vol.63
, Issue.2
, pp. 273-291
-
-
Yuan, K.-H.1
Bentler, P.M.2
-
35
-
-
0033719421
-
Wattch: A framework for architectural-level power analysis and optimizations
-
D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: A framework for architectural-level power analysis and optimizations, " in Proc. ISCA, 2000, pp. 83-94.
-
(2000)
Proc. ISCA
, pp. 83-94
-
-
Brooks, D.1
Tiwari, V.2
Martonosi, M.3
-
37
-
-
70350068439
-
Analyzing the impact of process variations on parametric measurements: Novel models and applications
-
S. Reda and S. Nassif, "Analyzing the impact of process variations on parametric measurements: Novel models and applications, " in Proc. DATE, 2009, pp. 375-380.
-
(2009)
Proc. DATE
, pp. 375-380
-
-
Reda, S.1
Nassif, S.2
-
38
-
-
34547268011
-
A general framework for spatial correlation modeling in VLSI design
-
DOI 10.1109/DAC.2007.375277, 4261296, 2007 44th ACM/IEEE Design Automation Conference, DAC'07
-
F. Liu, "A general framework for spatial correlation modeling in VLSI design, " in Proc. DAC, 2007, pp. 817-822. (Pubitemid 47130078)
-
(2007)
Proceedings - Design Automation Conference
, pp. 817-822
-
-
Liu, F.1
|