Implant damage and gate-oxide-edge effects on product reliability

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 481-484

  Lee, Yung Huei ^a   Nachman, Ramez ^a   Hu, Sam ^a   Mielke, Neal ^a   Liu, Jonathan ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC FIELDS; RELIABILITY; SILICON; STATIC RANDOM ACCESS STORAGE; VLSI CIRCUITS; CIRCUIT SIMULATION;

CIRCUIT SIMULATION; IMPLANT DAMAGE; MEMORY CELL; PRODUCT RELIABILITY;

LOGIC CIRCUITS; GATES (TRANSISTOR);

EDGE-DAMAGE; EDGE-EFFECTS; ENERGY IMPLANTS; GATE OXIDE; GATE OXIDE RELIABILITY; IMPLANT DAMAGE; OXIDE RELIABILITY; PROCESS SIMULATIONS; PRODUCT RELIABILITY; THIN GATE OXIDES;

EID: 21644481983     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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