Design of the Power6™ microprocessor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 96-97

  Friedrich, Joshua ^a   McCredie, Bradley ^a   James, Norman ^a   Huott, Bill ^a   Curran, Brian ^a   Fluhr, Eric ^a   Mittal, Gaurav ^a   Eddie, Chan ^a   Yuen, Chan ^a   Plass, Donald ^a   Sam, Chu ^a   Hung, Le ^a   Clark, Leo ^a   Ripley, John ^a   Taylor, Scott ^a   Dilullo, Jack ^a   Lanzerotti, Mary ^b  

^a IBM   (United States)

^b IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; NATURAL FREQUENCIES; PERMITTIVITY; SILICON ON INSULATOR TECHNOLOGY;

COPPER INTERCONNECTS; FREQUENCY OPERATION; POWER REDUCTION; SERVICEABILITY;

MICROPROCESSOR CHIPS;

EID: 34548817261     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373605     Document Type: Conference Paper

References (2)

1. E. Leobandung, H. Nayakama, D. Mocuta et al., "High Performance 65nm SOI Technology with Dual Stress Liner and Low Capacitance SRAM cell", 2005 Symp. VLSI Technology, pp. 126-127, June, 2005.
2. B. Curran, B. McCredie, L. Sigal, et al., "4GHz+ Low-Latency Fixed-Point and Binary Floating-Point Execution Units for the POWER6™ Processor", IEEE J. Solid-State Circuits, pp. 1728-1734, Feb., 2006.