Process challenges for integration of copper interconnects with low-k dielectrics

ECS Transactions

Volumn 35, Issue 4, 2011, Pages 687-699

  Gambino, J P ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL MECHANICAL POLISHING; COPPER; DIELECTRIC MATERIALS; INTEGRATED CIRCUIT INTERCONNECTS; INTEGRATION; MICROELECTRONICS; NANOTECHNOLOGY; SILICA; SILICON NITRIDE; SILICON OXIDES;

C-DOPED; CHEMICAL MECHANICAL POLISHING(CMP); COPPER INTERCONNECTS; CU-INTERCONNECTS; INTERCONNECT CAPACITANCE; INTERLEVEL DIELECTRIC; MICROELECTRONICS INDUSTRY; POROUS LOW-K DIELECTRICS;

LOW-K DIELECTRIC;

EID: 79960876091     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.3572313     Document Type: Conference Paper

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