Underfill characterization for low-k dielectric/Cu interconnect IC flip-chip package reliability

Proceedings - Electronic Components and Technology Conference

Volumn 1, Issue , 2004, Pages 767-769

  Tsao, Pei Haw ^a   Huang, Chender ^a   Lii, Mirng Ji ^a   Su, Bob ^a   Tsai, Nun Sian ^a  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

DELAMINATION; DIELECTRIC MATERIALS; PERMITTIVITY; STRESS ANALYSIS; THERMAL EXPANSION; YIELD STRESS;

PACKAGE INTEGRITY; STRESS-COUPLING INDEX; UNDERFILL MATERIALS; WAFER PROCESS TECHNOLOGY;

ELECTRONICS PACKAGING;

EID: 10444263716     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Mercado, Lei L. et al., "Impact of Flip-Chip packaging on Copper/Low-k Structure," IEEE Trans. on Advanced Packaging, Vol. 26, No. 4 (2003), pp.433-440.
2. th Electronic Components and Technology Conference, May 2000, pp. 1089-1094.
3. th Electronic Components and Technology Conference, May 2002, pp. 859-864.
4. Shim, Jong-Bo et al., "Mechanism of Die and Underfill Cracking in Flip Chip PBGA Package," 2000 International Symposium on Advanced Packaging Materials, pp. 201-205.
5. th Electronic Components and Technology Conference, May 2000, pp. 1215-1220.
6. th Electronic Components and Technology Conference, May 2001.