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Volumn , Issue , 2007, Pages 969-972
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32 nm node Ultralow-k(k=2.1)/Cu damascene multilevel interconnect using high-porosity (50 %) high-modulus (9 GPa) self-assembled porous silica
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Author keywords
[No Author keywords available]
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Indexed keywords
ADSORPTION;
ANNEALING;
COPPER;
ELECTRON DEVICES;
HARDENING;
NANOTECHNOLOGY;
POROUS MATERIALS;
SILANES;
SILICA;
SILICATE MINERALS;
SILICON COMPOUNDS;
TECHNOLOGY;
CU DAMASCENE;
HARDENING PROCESS;
INTEGRATION PROCESSES;
KEY TECHNOLOGIES;
LOW TEMPERATURE;
POROSITY MATERIAL;
POROUS DIELECTRICS;
POROUS SILICAS;
PROCESS TECHNOLOGIES;
RAPID ANNEALING;
SELF-ASSEMBLED;
SILYLATION;
TRENCH SIDEWALLS;
ULTRA LOW-K;
POROSITY;
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EID: 50249095654
PISSN: 01631918
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/IEDM.2007.4419115 Document Type: Conference Paper |
Times cited : (18)
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References (5)
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