-
1
-
-
41549139729
-
Digital circuit design trends
-
DOI 10.1109/JSSC.2008.917523
-
M. Horowitz, D. Stark, and E. Alon, "Digital circuit design trends," IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 757-761, Apr. 2008. (Pubitemid 351467583)
-
(2008)
IEEE Journal of Solid-State Circuits
, vol.43
, Issue.4
, pp. 757-761
-
-
Horowitz, M.1
Stark, D.2
Alon, E.3
-
2
-
-
31344455697
-
Ultra-Dynamic Voltage scaling (UDVS) using sub-threshold operation and local voltage dithering
-
DOI 10.1109/JSSC.2005.859886
-
B. H. Calhoun and A. P. Chandrakasan, "Ultra-dynamic voltage scaling (UDVS) using sub-threshold operation and local voltage dithering," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 238-245, Jan. 2006. (Pubitemid 43145981)
-
(2006)
IEEE Journal of Solid-State Circuits
, vol.41
, Issue.1
, pp. 238-245
-
-
Calhoun, B.H.1
Chandrakasan, A.P.2
-
3
-
-
85008035969
-
Minimum energy tracking loop with embedded DC-DC converter enabling ultra-low-voltage operation down to 250mVin 65 nm CMOS
-
Jan.
-
Y. K. Ramadass and A. P. Chandrakasan, "Minimum energy tracking loop with embedded DC-DC converter enabling ultra-low-voltage operation down to 250mVin 65 nm CMOS," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 256-265, Jan. 2008.
-
(2008)
IEEE J. Solid-State Circuits
, vol.43
, Issue.1
, pp. 256-265
-
-
Ramadass, Y.K.1
Chandrakasan, A.P.2
-
4
-
-
41549158226
-
A circuit for determining the optimal supply voltage to minimize energy consumption in LSI circuit operations
-
DOI 10.1109/JSSC.2008.917553
-
Y. Ikenaga, M. Nomura, Y. Nakazawa, and Y. Hagihara, "A circuit for determining the optimal supply voltage to minimize energy consumption in LSI circuit operations," IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 911-918, Apr. 2008. (Pubitemid 351464084)
-
(2008)
IEEE Journal of Solid-State Circuits
, vol.43
, Issue.4
, pp. 911-918
-
-
Ikenaga, Y.1
Nomura, M.2
Nakazawa, Y.3
Hagihara, Y.4
-
5
-
-
0034315851
-
Dynamic voltage scaled microprocessor system
-
DOI 10.1109/4.881202
-
T. D. Burd, T. A. Pering, A. J. Stratakos, and R. W. Brodersen, "A dynamic voltage scaled microprocessor system," IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1571-1580, Nov. 2000. (Pubitemid 32070549)
-
(2000)
IEEE Journal of Solid-State Circuits
, vol.35
, Issue.11
, pp. 1571-1580
-
-
Burd, T.D.1
Pering, T.A.2
Stratakos, A.J.3
Brodersen, R.W.4
-
6
-
-
19944427319
-
Dynamic voltage and frequency management for a low-power embedded microprocessor
-
Jan.
-
M. Nakai, S. Akui, K. Seno, T. Meguro, T. Seki, T. Kondo, A. Hashiguchi, H. Kawahara, K. Kumano, and M. Shimura, "Dynamic voltage and frequency management for a low-power embedded microprocessor," IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 28-35, Jan. 2005.
-
(2005)
IEEE J. Solid-State Circuits
, vol.40
, Issue.1
, pp. 28-35
-
-
Nakai, M.1
Akui, S.2
Seno, K.3
Meguro, T.4
Seki, T.5
Kondo, T.6
Hashiguchi, A.7
Kawahara, H.8
Kumano, K.9
Shimura, M.10
-
7
-
-
0036858657
-
A 32-bit powerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling
-
DOI 10.1109/JSSC.2002.803941
-
K. J. Nowka, G. D. Carpenter, E. W. MacDonald, H. C. Ngo, B. C. Brock, K. I. Ishii, T. Y. Nguyen, and J. L. Burns, "A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1441-1447, Nov. 2002. (Pubitemid 35432164)
-
(2002)
IEEE Journal of Solid-State Circuits
, vol.37
, Issue.11
, pp. 1441-1447
-
-
Nowka, K.J.1
Carpenter, G.D.2
MacDonald, E.W.3
Ngo, H.C.4
Brock, B.C.5
Ishii, K.I.6
Nguyen, T.Y.7
Burns, J.L.8
-
8
-
-
34347233021
-
In-situ delay characterization and local supply voltage adjustment for compensation of local parametric variations
-
DOI 10.1109/JSSC.2007.896695
-
M. Eireiner, S. Henzler, G. Georgakos, J. Berthold, and D. Schmitt- Landsiedel, "In-situ delay characterization and local supply voltage adjustment for compensation of local parametric variations," IEEE J. Solid-State Circuits, vol. 42, no. 7, pp. 1583-1592, Jul. 2007. (Pubitemid 47000223)
-
(2007)
IEEE Journal of Solid-State Circuits
, vol.42
, Issue.7
, pp. 1583-1592
-
-
Eireiner, M.1
Henzler, S.2
Georgakos, G.3
Berthold, J.4
Schmitt-Landsiedel, D.5
-
9
-
-
34249818812
-
Variation-aware adaptive voltage scaling system
-
DOI 10.1109/TVLSI.2007.896909
-
M. Elgebaly and M. Sachdev, "Variation-aware adaptive voltage scaling system," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 15, no. 5, pp. 560-571, May 2007. (Pubitemid 46853323)
-
(2007)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, vol.15
, Issue.5
, pp. 560-571
-
-
Elgebaly, M.1
Sachdev, M.2
-
10
-
-
34548812547
-
Adaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging
-
Feb.
-
J. Tschanz, N. S. Kim, S. Dighe, J. Howard, G. Ruhl, S. Vangal, S. Narendra, Y. Hoskote, H. Wilson, C. Lam, M. Shuman, C. Tokunaga, D. Somasekhar, S. Tang, D. Finan, T. Karnik, N. Borkar, N. Kurd, and V. De, "Adaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging," in IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 292-293.
-
(2007)
IEEE ISSCC Dig. Tech. Papers
, pp. 292-293
-
-
Tschanz, J.1
Kim, N.S.2
Dighe, S.3
Howard, J.4
Ruhl, G.5
Vangal, S.6
Narendra, S.7
Hoskote, Y.8
Wilson, H.9
Lam, C.10
Shuman, M.11
Tokunaga, C.12
Somasekhar, D.13
Tang, S.14
Finan, D.15
Karnik, T.16
Borkar, N.17
Kurd, N.18
De, V.19
-
11
-
-
28144454988
-
Sleep transistor circuits for fine-grained power switch-off with short power-down times
-
Feb.
-
S. Henzler, T. Nirschl, S. Skiathitis, J. Berthold, J. Fischer, P. Teichmann, F. Bauer,G. Georgakos, and D. Schmitt-Landsiedel, "Sleep transistor circuits for fine-grained power switch-off with short power-down times," in IEEE ISSCC Dig. Tech. Papers, Feb. 2005, pp. 302-303.
-
(2005)
IEEE ISSCC Dig. Tech. Papers
, pp. 302-303
-
-
Henzler, S.1
Nirschl, T.2
Skiathitis, S.3
Berthold, J.4
Fischer, J.5
Teichmann, P.6
BauerG, F.7
Georgakos, G.8
Schmitt-Landsiedel, D.9
-
12
-
-
62949189195
-
Design and implementation of fine-grain power gating with ground bounce suppression
-
Jan.
-
K. Usami, T. Shirai, T. Hashida, H. Masuda, S. Takeda, M. Nakata, N. Seki, H. Amano, M. Namiki, M. Imai, M. Kondo, and H. Nakamura, "Design and implementation of fine-grain power gating with ground bounce suppression," in Proc. Int. Conf. VLSI Des., Jan. 2009, pp. 381-386.
-
(2009)
Proc. Int. Conf. VLSI Des.
, pp. 381-386
-
-
Usami, K.1
Shirai, T.2
Hashida, T.3
Masuda, H.4
Takeda, S.5
Nakata, M.6
Seki, N.7
Amano, H.8
Namiki, M.9
Imai, M.10
Kondo, M.11
Nakamura, H.12
-
13
-
-
34547595879
-
A multi-mode power gating structure for low-voltage deep-submicron CMOS ICs
-
DOI 10.1109/TCSII.2007.894428
-
S. Kim, S. V. Kosonocky, D. R. Knebel, K. Stawiasz, and M. C. Papaefthymiou, "A multi-mode power gating structure for low-voltage deep-submicron CMOSICs," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 7, pp. 586-590, Jul. 2007. (Pubitemid 47193994)
-
(2007)
IEEE Transactions on Circuits and Systems II: Express Briefs
, vol.54
, Issue.7
, pp. 586-590
-
-
Kim, S.1
Kosonocky, S.V.2
Knebel, D.R.3
Stawiasz, K.4
Papaefthymiou, M.C.5
-
14
-
-
84861447641
-
Sleep transistor sizing using timing criticality and temporal currents
-
Jan.
-
A. Ramalingam, B. Zhang, A. Devgani, and D. Z. Pan, "Sleep transistor sizing using timing criticality and temporal currents," in Proc. Asia South Pacific Des. Autom. Conf. (ASPDAC), Jan. 2005, pp. 1094-1097.
-
(2005)
Proc. Asia South Pacific Des. Autom. Conf. (ASPDAC)
, pp. 1094-1097
-
-
Ramalingam, A.1
Zhang, B.2
Devgani, A.3
Pan, D.Z.4
-
15
-
-
46749132264
-
Automatic gate biasing of an SCCMOS power switch achieving maximum leakage reduction and lowering leakage current variability
-
Jul.
-
A. Valentian and E. Beigne, "Automatic gate biasing of an SCCMOS power switch achieving maximum leakage reduction and lowering leakage current variability," IEEE J. Solid-State Circuits, vol. 43, no. 7, pp. 1688-1698, Jul. 2008.
-
(2008)
IEEE J. Solid-State Circuits
, vol.43
, Issue.7
, pp. 1688-1698
-
-
Valentian, A.1
Beigne, E.2
-
16
-
-
67650218486
-
In-situ self-aware adaptive power control system with multi-mode power gating network
-
Sep.
-
W.-C. Hsieh and W. Hwang, "In-situ self-aware adaptive power control system with multi-mode power gating network," in Proc. IEEE Int. Syst.-on-Chip Conf. (SOCC), Sep. 2008, pp. 215-218.
-
(2008)
Proc. IEEE Int. Syst.-on-Chip Conf. (SOCC)
, pp. 215-218
-
-
Hsieh, W.-C.1
Hwang, W.2
-
17
-
-
28444494804
-
On-chip digital power supply control for system-on-chip applications
-
ISLPED'05 - Proceedings of the 2005 International Symposium on Low Power Electronics and Design
-
M. Meijer, J. P. de Gyvez, and R. Otten, "On-chip digital power supply control for system-on-chip applications," in Proc. Int. Symp. Low Power Electron. Des. (ISLPED), Aug. 2005, pp. 311-314. (Pubitemid 41731675)
-
(2005)
Proceedings of the International Symposium on Low Power Electronics and Design
, pp. 311-314
-
-
Meijer, M.1
De Gyvez, J.P.2
Otten, R.3
-
18
-
-
2442482721
-
Impact of power-supply noise on timing in high-frequency microprocessors
-
Feb.
-
M. Saint-Laurent and M. Swaminathan, "Impact of power-supply noise on timing in high-frequency microprocessors," IEEE Trans. Adv. Packag., vol. 27, no. 1, pp. 135-144, Feb. 2004.
-
(2004)
IEEE Trans. Adv. Packag.
, vol.27
, Issue.1
, pp. 135-144
-
-
Saint-Laurent, M.1
Swaminathan, M.2
-
19
-
-
36248949662
-
Validation of a full-chip simulation model for supply noise and delay dependence on average voltage drop with on-chip delay measurement
-
DOI 10.1109/TCSII.2007.901574
-
Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, "Validation of a full-chip simulation model for supply noise and delay dependence on average voltage drop with on-chip delay measurement," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 10, pp. 868-872, Oct. 2007. (Pubitemid 350123792)
-
(2007)
IEEE Transactions on Circuits and Systems II: Express Briefs
, vol.54
, Issue.10
, pp. 868-872
-
-
Ogasahara, Y.1
Enami, T.2
Hashimoto, M.3
Sato, T.4
Onoye, T.5
-
20
-
-
33846570414
-
Impact of supply voltage variations on full adder delay: Analysis and comparison
-
DOI 10.1109/TVLSI.2006.887809
-
M. Alioto and G. Palumbo, "Impact of supply voltage variations on full adder delay: Analysis and comparison," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 12, pp. 1322-1335, Dec. 2006. (Pubitemid 46181209)
-
(2006)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, vol.14
, Issue.12
, pp. 1322-1335
-
-
Alioto, M.1
Palumbo, G.2
-
21
-
-
0025415048
-
Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas
-
DOI 10.1109/4.52187
-
T. Sakurai and A. R. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas," IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 584-594, Apr. 1990. (Pubitemid 20701405)
-
(1990)
IEEE Journal of Solid-State Circuits
, vol.25
, Issue.2
, pp. 584-594
-
-
Sakurai Takayasu1
Newton A.Richard2
-
22
-
-
0033323845
-
Physical alpha-power law MOSFET model
-
DOI 10.1109/4.792617
-
K. A. Bowman, B. L. Austin, J. C. Eble, X. Tang, and J. D. Meindl, "A physical alpha-power law MOSFET model," IEEE J. Solid-State Circuits, vol. 34, no. 10, pp. 1410-1414, Oct. 1999. (Pubitemid 30524512)
-
(1999)
IEEE Journal of Solid-State Circuits
, vol.34
, Issue.10
, pp. 1410-1414
-
-
Bowman, K.A.1
Austin, B.L.2
Eble, J.C.3
Tang, X.4
Meindl, J.D.5
-
23
-
-
3042737073
-
-
Synopsys Mountain View CA, B-2008.12
-
Synopsys, Mountain View, CA, "PrimeTime User Guide: Fundamentals," B-2008.12, 2008.
-
(2008)
PrimeTime User Guide: Fundamentals
-
-
-
24
-
-
33750575807
-
Runtime leakage minimization through probability-aware optimization
-
DOI 10.1109/TVLSI.2006.884149, 1715345
-
D. Lee, D. Blaauw, and D. Sylvester, "Runtime leakage minimization through probability-aware optimization," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 10, pp. 1075-1088, Oct. 2006. (Pubitemid 44679636)
-
(2006)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, vol.14
, Issue.10
, pp. 1075-1088
-
-
Lee, D.1
Blaauw, D.2
Sylvester, D.3
-
25
-
-
34548854756
-
A distributed critical-path timing monitor for a 65 nm high-performance microprocessor
-
Feb.
-
A. Drake, R. Senger, H. Deogun, G. Carpenter, S. Ghiasi, T. Nguyen, N. James, M. Floyd, and V. Pokala, "A distributed critical-path timing monitor for a 65 nm high-performance microprocessor," in IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 398-399.
-
(2007)
IEEE ISSCC Dig. Tech. Papers
, pp. 398-399
-
-
Drake, A.1
Senger, R.2
Deogun, H.3
Carpenter, G.4
Ghiasi, S.5
Nguyen, T.6
James, N.7
Floyd, M.8
Pokala, V.9
-
26
-
-
54949122515
-
A statistical design-oriented delay variation model accounting for within-die variations
-
Nov.
-
M. H. Abu-Rahma and M. Anis, "A statistical design-oriented delay variation model accounting for within-die variations," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 27, no. 11, pp. 1983-1995, Nov. 2008.
-
(2008)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.
, vol.27
, Issue.11
, pp. 1983-1995
-
-
Abu-Rahma, M.H.1
Anis, M.2
-
27
-
-
34047189028
-
-
Cadence San Jose CA, 06.20-p006-1
-
Cadence, San Jose, CA, "SoC encounter," 06.20-p006-1, 2006.
-
(2006)
SoC Encounter
-
-
-
28
-
-
63449111317
-
A sub- μs wake-up time power gating technique with bypass power line for rush current support
-
Apr.
-
K. Kawasaki, T. Shiota, K. Nakayama, and A. Inoue, "A sub- μs wake-up time power gating technique with bypass power line for rush current support," IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1178-1183, Apr. 2009.
-
(2009)
IEEE J. Solid-State Circuits
, vol.44
, Issue.4
, pp. 1178-1183
-
-
Kawasaki, K.1
Shiota, T.2
Nakayama, K.3
Inoue, A.4
-
29
-
-
34347233021
-
In-situ delay characterization and local supply voltage adjustment for compensation of local parametric variations
-
DOI 10.1109/JSSC.2007.896695
-
M. Eireiner, S. Henzler, G. Georgakos, J. Berthold, and D. Schmitt- Landsiedel, "In-situ delay characterization and local supply voltage adjustment for compensation of local parametric variations," IEEE J. Solid-State Circuits, vol. 42, no. 7, pp. 1583-1592, Jul. 2007. (Pubitemid 47000223)
-
(2007)
IEEE Journal of Solid-State Circuits
, vol.42
, Issue.7
, pp. 1583-1592
-
-
Eireiner, M.1
Henzler, S.2
Georgakos, G.3
Berthold, J.4
Schmitt-Landsiedel, D.5
-
30
-
-
33645652998
-
A self-tuning DVS processor using delay-error detection and correction
-
Apr.
-
S. Das, D. Roberts, S. Lee, S. Pant, D. Blaauw, T. Austin, K. Flautner, and T. Mudge, "A self-tuning DVS processor using delay-error detection and correction," IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 792-804, Apr. 2006.
-
(2006)
IEEE J. Solid-State Circuits
, vol.41
, Issue.4
, pp. 792-804
-
-
Das, S.1
Roberts, D.2
Lee, S.3
Pant, S.4
Blaauw, D.5
Austin, T.6
Flautner, K.7
Mudge, T.8
-
31
-
-
58149218298
-
RazorII: In situ error detection and correction for PVT and SER tolerance
-
Jan.
-
S. Das, C. Tokunaga, S. Pant, W.-H. Ma, S. Kalaiselvan, K. Lai, D. M. Bull, and D. T. Blaauw, "RazorII: In situ error detection and correction for PVT and SER tolerance," IEEE J. Solid-State Circuits, vol. 44, no. 1, pp. 32-48, Jan. 2009.
-
(2009)
IEEE J. Solid-State Circuits
, vol.44
, Issue.1
, pp. 32-48
-
-
Das, S.1
Tokunaga, C.2
Pant, S.3
Ma, W.-H.4
Kalaiselvan, S.5
Lai, K.6
Bull, D.M.7
Blaauw, D.T.8
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