In-situ self-aware adaptive power control system with multi-mode power gating network

2008 IEEE International SOC Conference, SOCC

Volumn , Issue , 2008, Pages 215-218

  Hsieh, Wei Chih ^a   Hwang, Wei ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

90NM CMOS; ADAPTIVE POWER CONTROL; AREA OVERHEAD; CONTROL SIGNAL GENERATOR; DETECTION CIRCUITS; IN-SITU; MULTIMODE; OPERATING SPEED; POWER CONSUMPTION; POWER GATING; POWER REDUCTIONS; TEST BENCHES; VARIABLE THRESHOLDS; VOLTAGE SENSOR;

CHEMICAL PLANTS; CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; POWER CONTROL; SHIFT REGISTERS; SIGNAL GENERATORS;

ADAPTIVE CONTROL SYSTEMS;

EID: 67650218486     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOCC.2008.4641514     Document Type: Conference Paper

References (5)

1. M. Nakai, et al., "Dynamic Voltage and Frequency Management for a Low-Power Embedded Microprocessor," IEEE JSSC, Vol. 40, No. 1, pp. 28-35, Jan. 2005.
2. T. D. Burd, et al., "A Dynamic Voltage Scaled Microprocessor System," IEEE JSSC, Vol. 35, No. 11, pp. 1571-1580, Nov. 2000.
3. M. Saint-Laurent, et al., "Impact of Power-Supply Noise on Timing in High-Frequency Microprocessors," IEEE Trans. on Advanced Packaging, Vol. 27, No. 1, pp. 135-144, Feb. 2004.
4. Y. Ogasahara, et al., "Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop With On-Chip Delay Measurement," IEEE TCAS II, Vol. 54, No. 10, pp. 868-872, Oct. 2007.
5. S. Das, et al., "A Self-Tuning DVS Processor Using Delay-Error Detection and Correction," IEEE JSSC, Vol. 41, No. 4, pp. 792-804, Apr. 2006.