A circuit for determining the optimal supply voltage to minimize energy consumption in LSI circuit operations

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 4, 2008, Pages 911-918

  Ikenaga, Yoshifumi ^a   Nomura, Masahiro ^a   Nakazawa, Yoetsu ^a   Hagihara, Yasuhiko ^a  

^a NEC CORPORATION   (Japan)

Author keywords

CMOS; DVFS; Energy reduction; Power gating

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; ENERGY EFFICIENCY; ERROR ANALYSIS; LEAKAGE CURRENTS; VOLTAGE CONTROL;

ENERGY REDUCTION; POWER GATING;

DIGITAL INTEGRATED CIRCUITS;

EID: 41549158226     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.917553     Document Type: Conference Paper

References (9)

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