Sleep transistor circuits for fine-grained power switch-off with short power-down times

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Henzler, Stephan ^a   Nirschl, Thomas ^a,b   Skiathitis, Stylianos ^a,c   Berthold, Joerg ^b   Fischer, Juergen ^a   Teichmann, Philip ^a   Bauer, Florian ^a   Georgakos, Georg ^b   Schmitt Landsiede, Doris ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^b INFINEON TECHNOLOGIES AG   (Germany)

^c IBM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144454988     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/isscc.2005.1493989     Document Type: Conference Paper

References (8)

1. S. Mutoh et al., "IV Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS," IEEE J. Solid-State Circuits, vol. 30, no. 8, pp. 847-854, Aug., 1995.
2. J. Kao et al., "Transistor Sizing Issues and Tool For Multi-Threshold CMOS Technology," DAC, pp. 409-413, Jun., 1997.
3. S. Henzler et al., "Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched Circuits," PATMOS, pp. 789-798, Sept., 2004.
4. J. Tschanz et al., "Dynamic Sleep Transistor and Body Bias for Active Leakage Power Control of Microprocessors," IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1838-1845, Nov., 2003.
5. B. Calhoun et al., "Design Methodology for Fine Grained Leakage Control in MTCMOS," ISLPED, pp. 104-109, 2003.
6. H. Kawaguchi et al., "A Super Cut-Off CMOS Scheme for 0.5-V Supply Voltage with Picoampere Stand-By Current," IEEE J. Solid-State Circuits, vol. 35, no. 10, pp. 1498-1501, Oct., 2000.
7. S. Henzler et al., "Design Aspects and Technological Scaling Limits of ZigZag Circuit Block Switch-Off Schemes," VLSI-SOC, pp. 246-251, Nov., 2003.
8. S. Henzler et al., "Fast power-efficient circuit-block switch-off scheme," Electronics Letters, vol. 40, no. 2, pp. 103-104, Jan., 2004.