A multi-mode power gating structure for low-voltage deep-submicron CMOS ICs

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 54, Issue 7, 2007, Pages 586-590

  Kim, Suhwan ^a   Kosonocky, Stephen V ^b   Knebel, Daniel R ^b   Stawiasz, Kevin ^b   Papaefthymiou, Marios C ^c  

^a Seoul National University   (South Korea)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Deep submicrometer CMOS; ground bounce noise; low voltage; multi threshold CMOS (MTCMOS)

Indexed keywords

CUTOFF FREQUENCY; GATES (TRANSISTOR); SPURIOUS SIGNAL NOISE;

GROUND BOUNCE NOISE; POWER GATING STRUCTURE;

CMOS INTEGRATED CIRCUITS;

EID: 34547595879     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2007.894428     Document Type: Article

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