A statistical design-oriented delay variation model accounting for within-die variations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 27, Issue 11, 2008, Pages 1983-1995

  Abu Rahma, Mohamed H ^a,b   Anis, Mohab ^b  

^a QUALCOMM INC   (United States)

^b UNIVERSITY OF WATERLOO   (Canada)

Author keywords

Gate delay; Input slew; Intradie variations; Mismatch; Process variations; Random variations; Statistical modeling; Variation aware design; Within die (WID) variations

Indexed keywords

DESIGN; DIES; DIGITAL INTEGRATED CIRCUITS; GAS DYNAMIC LASERS; STATISTICAL METHODS; STATISTICS; TIME DELAY;

GATE DELAY; INPUT SLEW; INTRADIE VARIATIONS; MISMATCH; PROCESS VARIATIONS; RANDOM VARIATIONS; STATISTICAL MODELING; VARIATION-AWARE DESIGN; WITHIN-DIE (WID) VARIATIONS;

PROCESS ENGINEERING;

EID: 54949122515     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2008.2006096     Document Type: Article

References (31)

1. T. Mizuno, J. Okumtura, and A. Toriumi, "Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFET's," IEEE Trans. Electron Devices, vol. 41, no. 11, pp. 2216-2221, Nov. 1994.
2. D. Frank, R. Dennard, E. Nowak, P. Solomon, Y. Taur, and H.-S. Wong, "Device scaling limits of Si MOSFETs and their application dependencies," Proc. IEEE, vol. 89, no. 3, pp. 259-288, Mar. 2001.
3. J. Croon, S. Decoutere, W. Sansen, and H. Maes, "Physical modeling and prediction of the matching properties of MOSFETs," in Proc. 34th ESSDERC, 2004, pp. 193-196.
4. H. Masuda, S. Ohkawa, A. Kurokawa, and M. Aoki, "Challenge: Variability characterization and modeling for 65- to 90-nm processes," in Proc. CICC, 2005, pp. 593-599.
5. "The International Technology Roadmap for Semiconductors," ITRS Website. [Online]. Available: http://public.itrs.net
6. J. Tschanz, K. Bowman, and V. De, "Variation-tolerant circuits: Circuit solutions and techniques," in Proc. 42nd Annu. DAC, 2005, pp. 762-763.
7. A. Agarwal, D. Blaauw, and V. Zolotov, "Statistical timing analysis for intra-die process variations with spatial correlations," in Proc. IEEE/ACM ICCAD, 2003, pp. 900-907.
8. S. Sapatnekar, Timing. New York: Springer-Verlag, 2004.
9. A. Srivastava, D. Sylvester, and D. Blaauw, Statistical Analysis and Optimization for VLSI: Timing and Power (Series on Integrated Circuits and Systems). New York: Springer-Verlag, 2005.
10. M. Eisele, J. Berthold, D. Schmitt-Landsiedel, and R. Mahnkopf, "The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits," IEEE Trans. Veiy Large Scale Integr. (VLSI) Syst., vol. 5, no. 4, pp. 360-368, Dec. 1997.
11. T. Sakurai and A. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas," IEEE J. Solid State Circuits, vol. 25, no. 2, pp. 584-594, Apr. 1990.
12. H. Mahmoodi, S. Mukhopadhyay, and K. Roy, "Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits," IEEE J. Solid State Circuits, vol. 40, no. 9, pp. 1787-1796, Sep. 2005.
13. Y. Cao and L. T. Clark, "Mapping statistical process variations toward circuit performance variability: An analytical modeling approach," in Proc. 42nd Annu. DAC, 2005, pp. 658-663.
14. H. Masuda, S. Okawa, and M. Aoki, "Approach for physical design in sub-100 nm era," in Proc. IEEE ISCAS, 2005, pp. 5934-5937.
15. S. Borkar, T. Karnik, and V. De, "Design and reliability challenges in nanometer technologies," in Proc. 41st Annu. DAC, 2004, p. 75.
16. Y. Taur and T. H. Ning, Fundamentals of Modem VLSI Devices. New York: Cambridge Univ. Press, 1998.
17. K. Takeuchi, T. Tatsumi, and A. Furukawa, "Channel engineering for the reduction of random-dopant-placement-induced threshold voltage fluctuations," in IEDM Tech. Dig., 1996, pp. 841-844.
18. B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, 2000.
19. Y. Cheng and C. Hu, MOSFET Modeling and BSIM User Guide. Norwell, MA: Kluwer, 1999.
20. J. A. Croon, W. Sansen, and H. E. Maes, Matching Properties of Deep Sub-Micron MOS Transistors. New York: Springer-Verlag, 2005.
21. T.-C. Chen, "Where CMOS is going: Trendy hype versus real technology," in Proc. Dig. Tech. Papers ISSCC, 2006, pp. 22-28.
22. P. Kinget, "Device mismatch and tradeoffs in the design of analog circuits," IEEE J. Solid State Circuits, vol. 40, no. 6, pp. 1212-1224, Jun. 2005.
23. K. Shinkai, M. Hashimoto, A. Kurokawa, and T. Onoye, "A gate delay model focusing on current fluctuation over wide-range of process and environmental variability," in Proc. IEEE/ACM ICCAD, 2006, pp. 47-53.
24. N. H. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 3rd ed. Reading, MA: Addison-Wesley, 2004.
25. W. Liu, MOSFET Modeling for SPICE Simulation, Including BSIM3v3 and BSIM4. Hoboken, NJ: Wiley, 2001.
26. N. Hedenstierna and K. Jeppson, "CMOS circuit speed and buffer optimization," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. CAD-6, no. 3, pp. 270-281, Mar. 1987.
27. J. M. Daga and D. Auvergne, "A comprehensive delay macro modeling for submicrometer CMOS logics," IEEE J. Solid State Circuits, vol. 34, no. 1, pp. 42-55, Jan. 1999.
28. M. Pelgrom, H. Tuinhout, and M. Vertregt, 'Transistor matching in analog CMOS applications," in IEDM Tech. Dig., 1998, pp. 915-918.
29. C. Piguet, Low-Power CMOS Circuits: Technology, Logic Design and CAD Tools. Boca Raton, FL: CRC Press, 2005.
30. K. Bowman, S. Duvall, and J. Meindl, "Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration," IEEE J. Solid State Circuits, vol. 37, no. 2, pp. 183-190, Feb. 2002.
31. V. Nguyen Hoang, A. Kumar, and P. Christie, "The impact of back-end-of-line process variations on critical path timing," in Proc. IITC, 2006, pp. 193-195.