Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with on-Chip Delay Measurement

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 54, Issue 10, 2007, Pages 868-872

  Ogasahara, Yasuhiro ^a   Enami, Takashi ^a   Hashimotc, Masanori ^a   Sato, Takashi ^b   Onoye, Takao ^a  

^a OSAKA UNIVERSITY   (Japan)

^b TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

Delay estimation; full chip simulation; linear element model; power supply noise; transistor model

Indexed keywords

ELECTRIC CURRENTS; ELECTRIC POTENTIAL; GATES (TRANSISTOR); RESISTORS;

FULL-CHIP SIMULATION; GATE DELAY; NANO-METER TECHNOLOGY; POWER INTEGRITY;

TRANSISTORS;

EID: 36248949662     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2007.901574     Document Type: Article

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