Impact of power-supply noise on timing in high-frequency microprocessors

IEEE Transactions on Advanced Packaging

Volumn 27, Issue 1, 2004, Pages 135-144

  Saint Laurent, Martin ^a   Swaminathan, Madhavan ^b  

^a INTEL CORPORATION   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Circuit simulation; Clock distribution; Clock jitter; Interconnect; Power distribution; Power supply noise; Timing analysis

Indexed keywords

ELECTRIC POWER SUPPLIES TO APPARATUS; MICROPROCESSOR CHIPS; SPURIOUS SIGNAL NOISE; TIMING CIRCUITS;

HIGH FREQUENCY MICROPROCESSORS; POWER SUPPLY NOISE;

ELECTRONICS PACKAGING;

EID: 2442482721     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2004.825480     Document Type: Article

References (25)

1. J. H. Stathis, "Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits," IEEE Trans. Device Mater. Rel., vol. 1, pp. 43-59, Mar. 2001.
2. T. Ichikawa and M. Sasaki, "A new analytical model of SRAM cell stability in low-voltage operation," IEEE Trans. Electron Devices, vol. 43, pp. 54-61, Jan. 1996.
3. L.-R. Zheng and H. Tenhunen, "Fast modeling of core switching noise on distributed LRC power grid in ULSI circuits," IEEE Trans. Adv. Packag., vol. 24, pp. 245-254, Aug. 2001.
4. A. Kabbani and A. J. Al-Khalili, "Estimation of ground bounce effects on CMOS circuits," IEEE Trans. Comp. Packag. Technol., vol. 22, pp. 316-325, June 1999.
5. H.-R. Cha and O.-K. Kwon, "An analytical model of simultaneous switching noise in CMOS sysetms," IEEE Trans. Adv. Packag., vol. 23, pp. 62-68, Feb. 2000.
6. A. Dharchoudhury, R. Panda, D. Blaauw, and R. Vaidyanathan, "Design and analysis of power distribution networks in PowerPC microprocessors," in Proc. Design Automat. Conf., 1998.
7. M. Zhao, R. V. Panda, S. S. Sapatnekar, and D. Blaauw, "Hierarchical analysis of power distribution networks," IEEE Trans. Computer-Aided Design, vol. 21, pp. 159-168, Feb. 2002.
8. H. H. Chen and J. S. Neely, "Interconnect and circuit modeling techniques for full-chip power supply noise analysis," IEEE Trans. Comp., Packag., Manufact. Technol. B, vol. 21, pp. 209-215, Aug. 1998.
9. T. Rahal-Arabi, G. Taylor, M. Ma, and C. Webb, "Design and validation of the Pentium III and Pentium 4 processors power delivery," in Proc. Symp. VLSI Circuits, 2002.
10. ____, "Design and validation of the core and IO's decoupling of the Pentium III and Pentium 4 processors," Elect. Perform. Electron. Packag., 2002.
11. Y.-M. Jiang and K.-T. Cheng, "Vector generation for power supply noise estimation and verification of deep submicron designs," IEEE Trans. VLSI Syst., vol. 9, pp. 329-340, Apr. 2001.
12. S. R. Nassif and J. N. Kozhaya, "Fast power grid stimulation," in proc. ACM/IEEE Design Automat. Conf., 2000.
13. R. Panda, D. Blaauw, R. Chaudhry, V. Zolotov, B. Young, and R. Ramaraju, "Model and analysis for combined package and on-chip power grid simulation," in Proc. Int. Symp. Low-Power Electron. Design, 2000.
14. Y.-M. Jiang and K.-T. Cheng, "Analysis of performance impact caused by power supply noise in deep submicron devices," in Proc. Design Automat. Conf., 1999.
15. T. Sakurai and A. R. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas," IEEE J. Solid-State Circuits, vol. 25, pp. 584-594, Apr. 1990.
16. ____, "A simple MOSFET model for circuit analysis," IEEE Trans. Electron. Devices, vol. 38, pp. 887-894, Apr. 1991.
17. L. H. Chen, M. Marek-Sadowska, and F. Brewer, "Buffer delay change in the presence of power and ground noise," IEEE Trans. VLSI Syst., vol. 11, pp. 461-473, June 2003.
18. S. Thompson et al., "An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7-1.4 V," in Proc. IEEE Int. Electron Devices Meeting, 2001.
19. N. H. E. West and K. Eshraghian, Principles of CMOS VLSI Design: a Sysetm Perspective, 2nd ed. Reading, MA: Addison-Wesley, 1993, ch. 8.
20. R. Ho, K. W. Mai, and M. A. Horowitz, "The future of wires," Proc. IEEE, vol. 89, pp. 490-504, Apr. 2001.
21. P. J. Restle et al., "A clock distribution network for microprocessors," IEEE J. Solid-State Circuits, vol. 36, pp. 792-799, May 2001.
22. ____, "The clock distribution of the Power4 microprocessor," in Proc. IEEE Int. Solid-State Circuits Conf., 2002.
23. J. A. Davis, "A hierarchy of interconnect limits and opportunities for gigascale integration," Ph.D. dissertation, Georgia Inst. of Technol., Atlanta, GA, 1999.
24. D. Sylvester and C. Yu, "Analytical modeling and characterization of deep-submicrometer interconnect," Proc. IEEE, vol. 89, pp. 634-664, May 2001.
25. Intel Corporation. (2002, May) Intel Pentium 4 Processor With 512-kB L2 Cache on 0.13 Micron Process at 2 GHz, 2.20 GHz, 2.26 GHz, 2.40 GHz, and 2.53 GHz. [Online] http://developer.intel.com