3D integration technology and reliability

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2011, Pages

  Koyanagi, Mitsumasa ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

3D LSI; Cu contamination; Mechanical stress; Microbump; TSV

Indexed keywords

3-D INTEGRATION; 3D HETEROGENEOUS INTEGRATION; 3D LSI; C-T CURVE; GENERATION LIFETIME; HIGH-DENSITY METAL; MECHANICAL STRAIN; MECHANICAL STRESS; MICRO-BUMPS; MINORITY CARRIER; SILICON SUBSTRATES; THIN WAFERS; THREE DIMENSIONAL (3D) INTEGRATION; THROUGH SILICON VIAS; TSV; WAFER THINNING;

ANNEALING; CONTAMINATION; CRYSTAL DEFECTS; INTEGRATION; METAL ANALYSIS; MOS CAPACITORS; RELIABILITY; SILICON WAFERS; STRESSES; WAFER BONDING;

THREE DIMENSIONAL;

EID: 79959312380     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IRPS.2011.5784496     Document Type: Conference Paper

References (31)

1. M. Koyanagi, "Roadblocks in Achieving Three-Dimensional LSI," Proc. 8th Symposium on Future Electron Devices, pp.50-60, 1989.
2. H. Takata, M. Koyanagi et al., "A novel fabrication technology for optically interconnected three-dimensional LSI by wafer aligning and bonding technique," Int. Semiconductor Device Research Symposium, pp.327-330, 1991.
3. T. Matsumoto, M. Koyanagi et al., "Three-dimensional integration technology based on wafer bonding technique using micro-bumps," Conf. on Solid State Devices and Materials (SSDM), pp.1073-1074, 1995.
4. M. Koyanagi, H. Kurino, K-W Lee, K. Sakuma and H. Itani, "Future system-on-silicon LSI chips," IEEE MICRO, 18 (4), pp.17-22, 1998.
5. T. Matsumoto, M. Koyanagi et al., "New three-dimensional wafer bonding technology using the adhesive injection method," Jpn. J. Appl. Phys., 1 (3B), pp.1217-1221, 1998.
6. A. Fan, A. Rahman, and R. Reif, "Copper wafer bonding," Electrochem. Solid State Lett., vol.2, no.10, pp.534-536, 1999.
7. H. Kurino, M. Koyanagi et al., "Intelligent image sensor chip with three dimensional structure," Int. Electron Devices Meeting (IEDM) Dig., pp.879-882, 1999.
8. K W. Lee, M. Koyanagi, "Three-dimensional shared memory fabricated using wafer stacking technology," Int. Electron Devices Meeting (IEDM) Dig., pp.165-168, 2000.
9. M. Koyanagi et al., "Neuromorphic vision chip fabricated using three-dimensional integration technology," Int, Solid State Circuits Conf. (ISSCC) Dig, pp.270-271, 2001.
10. J. A. Davis et al., "Interconnect limits on gigascale integration (GSI) in the 21st century," Proc. IEEE, vol.89, no.3, pp.305-324, 2001.
11. P. Ramm et al, "Interchip via technology for vertical system integration," Int. Interconnect Technology Conf. (IITC), pp.160-162, 2001.
12. J. Burns et al., "Three-dimensional integrated circuits for low-power, high-bandwidth systems on a chip," Int, Solid State Circuits Conf. (ISSCC) Dig., pp.268-269, 2001.
13. T. Ono, M. Koyanagi et al., "Three-dimensional processor system fabricated by wafer stacking technology," Int. Symp. on Low-Power and High-Speed Chips (COOL Chips), pp.186-193, 2002.
14. J.-Q. Lu et al., "Evaluation procedures for wafer bonding and thinning of interconnect test structure for 3D ICs," Int. Interconnect Technology Conf. (IITC), pp.74-76, 2003.
15. B. Swinnen et al., "3D integration by Cu-Cu thermocompression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias", Int. Electron Devices Meeting (IEDM) Dig., pp. 371-374, 2006.
16. M. Koyanagi et al., "Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections," IEEE Trans. on Electron Devices, vol. 53, No. 11, pp. 2799-2808, 2006.
17. Jan Van Olmen et al., "3D Stacked IC Demonstration using a Trough Silicon Via First Approach", Int. Electron Devices Meeting (IEDM) Dig., pp.603-606, 2008.
18. Uksong Kang et al., "8Gb 3D DDR3 DRAM Using Through-Silicon-Via Technology," Proc. IEEE Int, Solid State Circuits Conf. (ISSCC) Dig., pp.130-131, 2009.
19. M. Koyanagi, T. Fukushima and T. Tanaka, "High-Density Through Silicon Vias for 3-D LSIs," Proceedings of THE IEEE, Vol.97. No.1, pp.49-59, (2009).
20. T. Fukushima, Y. Yamada, H. Kikuchi and M. Koyanagi, "New Three- Dimensional Integration Technology Using Self-Assembly Technique," Int. Electron Devices Meeting IEDM) Dig., pp.359-362, 2005.
21. T. Fukushima, M. Koyanagi et al., "New Three-Dimensional Integration Technology Based on Reconfigured Wafer-on-Wafer Bonding Technique," Int. Electron Devices Meeting (IEDM) Dig., pp.985-988, 2007.
22. T. Fukushima, M. Koyanagi, "Three-Dimensional Integration Technology Based on Reconfigured Wafer-to-Wafer and Multichip-to-Wafer Stacking Using Self-Assembly Method," Int. Electron Devices Meeting (IEDM) Dig., pp.349-352, 2009.
23. K-W Lee, M. Koyanagi et al., "3D Heterogeneous Opto-Electronic Integration Technology for System-on-Silicon (SOS)," Int. Electron Devices Meeting (IEDM) Dig., pp.531-534, 2009.
24. T. Fukushima, E. Iwata, K.-W. Lee, T. Tanaka and M. Koyanagi, "Self-Assembly Technology for Reconfigured Wafer-to-Wafer 3D Integration," Electronic Components and Technology Conference (ECTC), pp.1050-1053, 2010.
25. Kang-Wook Lee, M. Koyanagi et al., "Three-Dimensional Hybrid Integration Technology of CMOS, MEMS, and Photonics Circuits for Optoelectronic Heterogeneous Integrated Systems," IEEE Trans. on Electron Devices,Vol.58, No3, March, 2011.
26. M. Murugesan, M. Koyanagi et al., "Impact of Remnant Stress/Strain and Metal Contamination in 3D-LSIs with Through-Si Vias Fabricated by wafer Thinning and Bonding," Int. Electron Devices Meeting (IEDM) Dig., pp.361-364, 2009.
27. C. Okoro et al., "Extraction of the Appropriate Material Property for Realistic Modeling of Through-Silicon-Vias using μ-Raman Spectroscopy," Int. Interconnect Technology Conf. (IITC), pp.16-18, 2008.
28. A. Mercha et al., "Comprehensive Analysis of the Impact of Single and Arrays of Through Silicon Vias Induced Stress on High-k / Metal Gate CMOS Performance," Int. Electron Devices Meeting (IEDM) Dig., pp.26-29, 2010.
29. M. Murugesan, M. Koyanagi et al., "Wafer Thinning, Bonding, and Interconnects Induced Local Strain/Stress in 3D-LSIs with Fine-Pitch High-Density Microbumps and Through-Si Vias," Int. Electron Devices Meeting (IEDM),pp.30-33, 2010.
30. Jichel Bea, K. W. Lee, T. Fukushima, T. Tanaka and M. Koyanagi, "Evaluation of Cu Contamination at Backside Surface of Thinned Wafer in 3-D Integration by Transient-Capacitance Measurement," IEEE Electron Device Lett., Vol.32, No.1, January, pp.66-68, 2011.
31. K. Hozawa, K. Takeda and K. Torii, Symp. on VLSI Tech. Dig., pp.172-173, 2009.