Evaluation of Cu contamination at backside surface of thinned wafer in 3-D integration by transient-capacitance measurement

IEEE Electron Device Letters

Volumn 32, Issue 1, 2011, Pages 66-68

  Bea, Jichel ^a   Lee, Kangwook ^a   Fukushima, Takafumi ^a   Tanaka, Tetsu ^a   Koyanagi, Mitsumasa ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

Capacitancetime (C =t); charge carrier lifetime; Cu diffusion; three dimensional (3 D) LSI

Indexed keywords

3-D INTEGRATION; CAPACITANCETIME (C =T); CU ATOMS; CU DIFFUSION; DEVICE RELIABILITY; FRONT SURFACES; GENERATION LIFETIME; SURFACE CONCENTRATION; THREE-DIMENSIONAL (3-D) LSI;

CAPACITANCE MEASUREMENT; CAPACITORS; MOS CAPACITORS; SILICON COMPOUNDS; SILICON WAFERS; THREE DIMENSIONAL;

CARRIER LIFETIME;

EID: 78650863245     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2010.2087004     Document Type: Conference Paper

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