3D stacked IC demonstration using a through silicon via first approach

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2008, Pages

  Van Olmen, J ^a   Mercha, A ^a   Katti, G ^b   Huyghebaert, C ^a   Van Aelst, J ^a   Seppala, E ^a   Chao, Zhao ^a   Armini, S ^a   Vaes, J ^a   Teixeira, R Cotrin ^a   Van Cauwenberghe, M ^a   Verdonck K Verhemeldonck, P ^a   Jourdain, A ^a   Ruythooren, W ^a   De Potter De Ten Broeck, M ^a   Opdebeeck, A ^a   Chiarella, T ^a   Parvais, B ^a   Debusschere, I ^a   Hoffmann, T Y ^a   De Wachter, B ^a   Dehaene, W ^b   Stucchi, M ^a   Rakowski, M ^a   Soussan, Ph ^a   Cartuyvels, R ^a   Beyne, E ^a   Biesemans, S ^a   Swinnen, B ^a   more..

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATED CIRCUITS; 3D STACKING; CMOS PROCESS; DIE STACKING; PROCESS IMPACTS; RING OSCILLATORS; THERMO COMPRESSIONS; THROUGH-SILICON VIAS; THROUGH-SILICON-VIA;

DIES; ELECTRIC NETWORK TOPOLOGY; ELECTRON DEVICES; INTEGRATED CIRCUITS; LANDING; SILICON WAFERS; WAFER BONDING;

SEMICONDUCTING SILICON COMPOUNDS;

EID: 64549088356     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2008.4796763     Document Type: Conference Paper

References (7)

1. E. Beyne, "3D interconnection and packaging: impending reality or still a dream?", Digest of Technical Papers, International Solid-State Conference 2004, IEEE-New Jersey, pp.138-145.
2. rd dimension for system integration", Technical Digest of the International Interconnect Technology Conference 2006, IEEE - New Jersey, pp. 1-5.
3. E. Beyne, "System-Driven Approaches to 3D Integration", Proceedings 4th International Symposium on Microelectronics and Packaging, Seoul, South Korea,Sep. 28, 2005.
4. B. Swinnen et al., "3D integration by Cu-Cu thermocompression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias", Technical Digest of the International Electron Device Meeting 2006, pp. 371-374.
5. A. Jourdain, S. Stoukatch, P. De Moor, W. Ruythooren, S. Pargfrieder, B. Swinnen and E. Beyne," Simultaneous Cu-Cu and Compliant Dielectric Bonding for 3D Stacking of ICs", Technical Digest of the International Interconnect Technology Conference 2007, IEEE-New Jersey, pp. 207-209.
6. K. De Munck, T. Chiarella, P. De Moor, B. Swinnen, C. Van Hoof, "Influence of extreme thinning on 130nm standard CMOS devices for 3D Integration", IEEE Electron Device Letters, Vol.29, No.4, 2008, pp. 322-324.
7. C. Okoro, Y. Yang, B. Vandevelde, B. Swinnen, D. Vandepitte, B. Verlinden, I de Wolf, "Extraction of the appropriate material property for realistic modeling of Through-Silicon-Vias using μ,-Raman Spectroscopy", Technical Digest of the International Interconnect Technology Conference 2008, IEEE-New Jersey, pp. 16-18.