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Volumn , Issue , 2010, Pages
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Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance
a a a a e a b c a a a a a a a a d e a a more.. |
Author keywords
[No Author keywords available]
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Indexed keywords
3-D INTEGRATION;
3D FLOW;
COMPREHENSIVE ANALYSIS;
COMPREHENSIVE STUDIES;
EXPERIMENTAL ASSESSMENT;
FRONT-END DEVICES;
INDUCED STRESS;
KEEP-OUT-ZONE;
KEY CONSTRAINTS;
MECHANICAL STRESS;
METAL GATE;
POWER EFFICIENCY;
SILICON AREA;
STRESS DISTRIBUTION;
STRESS-INDUCED;
THEORETICAL APPROACH;
THROUGH SILICON VIAS;
DIGITAL CIRCUITS;
ELECTRON DEVICES;
STRESS CONCENTRATION;
THREE DIMENSIONAL;
DIGITAL DEVICES;
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EID: 79951833703
PISSN: 01631918
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/IEDM.2010.5703278 Document Type: Conference Paper |
Times cited : (80)
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References (6)
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