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Volumn , Issue , 2010, Pages

Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; 3D FLOW; COMPREHENSIVE ANALYSIS; COMPREHENSIVE STUDIES; EXPERIMENTAL ASSESSMENT; FRONT-END DEVICES; INDUCED STRESS; KEEP-OUT-ZONE; KEY CONSTRAINTS; MECHANICAL STRESS; METAL GATE; POWER EFFICIENCY; SILICON AREA; STRESS DISTRIBUTION; STRESS-INDUCED; THEORETICAL APPROACH; THROUGH SILICON VIAS;

EID: 79951833703     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2010.5703278     Document Type: Conference Paper
Times cited : (80)

References (6)
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.