A fully characterizable asynchronous multiphase delay generator

IEEE Transactions on Nuclear Science

Volumn 58, Issue 2, 2011, Pages 418-425

  Zlatanski, Martin ^a   Uhring, Wilfried ^a   Le Normand, Jean Pierre ^a   Mathiot, Daniel ^a  

^a UNIVERSITÉ DE STRASBOURG   (France)

Author keywords

Delay locked loop (DLL); jitter; multiphase delay generator; phase noise; streak camera; temporal axis; voltage controlled delay line (VCDL)

Indexed keywords

ANALOG MEMORIES; ASYNCHRONOUS OPERATION; CMOS TECHNOLOGY; DELAY AND JITTER; DELAY VARIATION; DELAY-LOCKED LOOPS; DYNAMIC RANGE; JITTER PERFORMANCE; MEMORY BLOCKS; MULTIPHASE DELAY GENERATOR; REFERENCE CLOCK; SINGLE STAGE; TEMPORAL AXIS; TEMPORAL DYNAMICS; TWO DELAYS; VOLTAGE-CONTROLLED DELAY LINE (VCDL); VOLTAGE-CONTROLLED DELAY LINES;

CAMERAS; CMOS INTEGRATED CIRCUITS; ELECTRIC DELAY LINES; MIRRORS; PHASE NOISE; STREAK CAMERAS; WAVES;

JITTER;

EID: 79954608050     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2011.2106141     Document Type: Article

References (41)

1. D. J. Foley and M. P. Flynn, "CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator," IEEE J. Solid-State Circuits, vol. 36, pp. 417-423, Mar. 2001. (Pubitemid 32302982)
2. C. Kim, I. C. Hwang, and S. M. Kang, "Low-power small-area μ7.28ps jitter 1 GHz DLL-based clock generator," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1414-1420, Nov. 2002. (Pubitemid 35432161)
3. S. Sidiropoulos and M. A. Horowitz, "A semidigital dual delay-locked loop," IEEE J. Solid-State Circuits, vol. 32, no. 11, pp. 1683-1692, Nov. 1997. (Pubitemid 127606775)
4. S. J. Kim, S. H. Hong, J.-K. Wee, J. H. Cho, P. S. Lee, J. H. Ahn, and J. Y. Chung, "A low-jitter wide-range skew-calibrated dual-loop DLL using antifuse circuitry for high-speed DRAM," IEEE J. Solid-State Circuits, vol. 37, no. 6, pp. 726-734, Jun. 2002. (Pubitemid 34811872)
5. M. J. Lee, W. J. Dally, J.W. Poulton, P. Chiang, and S. E. Greenwood, "An 84-mW 4-Gb/s clock and data recovery circuit for serial link applications," in Proc. Symp. VLSI Circuits, 2001, pp. 149-152. (Pubitemid 32957493)
6. V. Hakkarainen, A. Rantala, M. Aho, J. Riikonen, D. Gomes-Martin, M. Aberg, and K. Halonen, "A 10-bit, 1.8-GS/s time-interleaved pipeline ADC," in Proc. 14th IEEE Int. Conf. Electron., Circuits Syst., Dec. 2007, pp. 673-676.
7. D. Santos, S. Dow, J. Flasck, and M. Levi, "A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip," IEEE Trans. Nucl. Sci., vol. 43, pp. 1717-1719, Jun. 1996. (Pubitemid 126775982)
8. C.-S. Hwang, P. Chen, and H.-W. Tsao, "A high-precision time-todigital converter using a two-level conversion scheme," IEEE Trans. Nucl. Sci., vol. 51, no. 4, pp. 1349-1352, Aug. 2004.
9. B. Kim, T. C.Weigandt, and P. R. Gray, "PLL/DLL system noise analysis for low jitter clock synthesizer design," IEEE Trans. Circuits Syst., vol. 4, pp. 31-34, 30 May-2 Jun. 1994.
10. A. Hajimiri, S. Limotyrakis, and T. H. Lee, "jitter and phase noise in ring oscillators," IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 790-804, Jun. 1999.
11. R. C.-H. Chang, H.-M. Chen, and P.-J. Huang, "A multiphase-output delay-locked-loop with a novel start-controlled phase/frequency detector," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 10, pp. 2443-2490, Oct. 2008.
12. O. Bourrion and L. Gallin-Martel, "An integrated CMOS time-to-digital converter for coincidence detection in a liquid Xenon PET prototype," Nucl. Instrum. Methods Phys. Res. Sect. A, vol. 563, no. 1, pp. 100-103, Jul. 2006. (Pubitemid 43866983)
13. J. Christiansen, "An integrated CMOS 0.15 ns digital timing generator for TDC's and clock distribution systems," IEEE Trans. Nucl. Sci., vol. 42, no. 4, pp. 753-757, Aug. 1995.
14. M. Zlatanski, W. Uhring, J.-P. Le Normand, C.-V. Zint, and D. Mathiot, "Streak camera in standard (Bi)CMOS (bipolar complementary metal-oxide-semiconductor) technology," Measur. Sci. Technol., vol. 21, p. 115203, 2010.
15. Optronis GmbH, Kehl, Germany, "Optronis GmbH," 2010. [Online]. Available: www.optronis.com/streak-kameras
16. T. Zhu, J. M. Yang, B. Deng, D. Yang, X. A. He, and Z. B. Wang, "X-ray streak camera sweep speed calibration," Rev. Scient. Instrum., vol. 81, p. 056108, 2010.
17. F. Morel, J.-P. Le Normand, C.-V. Zint, W. Uhring, Y. Hu, and D. Mathiot, "A new spatiotemporal CMOS imager with analog accumulation capability for nanosecond low-power pulse detections," IEEE Sensors J., vol. 6, no. 5, pp. 1200-1208, May 2006.
18. S. Kleinfelder, S.-H. Wood Chiang, W. Huang, A. Shah, and K. Kwiatkowski, "High-speed, high dynamic-range optical sensor arrays," IEEE Trans. Nucl. Sci., vol. 56, no. 3, pp. 1069-1075, Jun. 2009.
19. M. Zlatanski, W. Uhring, J.-P. Le Normand, C.-V. Zint, and D. Mathiot, "12- 7.14 GS/s rate time-resolved BiCMOS imager," in Proc. 8th IEEE Int. NEWCAS Conf., Jun. 2010, pp. 97-100.
20. H. Furtado, J. Schrader, A. Marchioro, and P. Moreira, "Delay 25 an ASIC for timing adjustment in LHC," in Proc. 11thWorkshop Electron. for LHC Future Experiments, Sep. 2005, pp. 148-152.
21. M. Stojčev and G. Jovanović, "Clock aligner based on delay locked loop with double edge synchronization," Microelectron. Reliab., vol. 48, no. 1, pp. 158-166, Jan. 2008. (Pubitemid 351260083)
22. N. R. Mahapatra, A. Tareen, and S. V. Garimella, "Comparison and analysis of delay elements," in Proc. IEEE 45th Midw. Symp. Circuits Syst., Aug. 2002, vol. 2, pp. 473-476.
23. H.-H. Chang, J.-W. Lin, and S.-I. Liu, "A wide-range delay-locked loop with a fixed latency of one clock cycle," IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1021-1027, Aug. 2002.
24. Comsol Group, Burlington, MA, "Comsol homepage," 2010. [Online]. Available: www.comsol.com
25. Cadence Design Systems, Inc., San Jose, CA, "Cadence homepage," 2010. [Online]. Available: www.cadence.com
26. A. Abidi, "Phase noise and jitter in CMOS ring oscillators," IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1803-1816, Aug. 2006. (Pubitemid 44192106)
27. T. C. Weigandt, B. Kim, and P. R. Gray, "Analysis of timing jitter in CMOS ring oscillators," in Proc. IEEE Int. Symp. Circuits Syst., Jun. 1994, vol. 4, pp. 27-30.
28. R. C. H. van de Beek, E. A. M. Klumperink, C. S. Vaucher, and B. Nauta, "Low-jitter clock multiplication: A comparison between PLLs and DLLs," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 49, no. 8, pp. 555-566, Aug. 30, 2002.
29. E. Rubiola and V. Giordano, "Phase Noise Metrology," in Lecture Notes in Physics. New York: Springer, 1999, vol. 550, pp. 189-215.
30. F. L.Walls and A. DeMarchi, "RF spectrum of a signal after frequency multiplication; measurement and comparison with a simple calculation," IEEE Trans. Instrum. Meas., vol. IM-24, no. 3, pp. 210-217, Sep. 1975.
31. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433-1440, May 1989.
32. B. Linares-Barranco and T. Serrano-Gotarredona, "On an efficient implementation of the distance term in Pelgrom's mismatch model," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 26, no. 8, pp. 1534-1538, Aug. 2007. (Pubitemid 47117382)
33. P. G. Drennan, "Device mismatch in BiCMOS technologies," in Proc. Bipolar/BiCMOS Circuits Technol. Meet., 2002, pp. 104-111. (Pubitemid 35406524)
34. R. C. Jaeger, R. Ramani, and J. C. Suling, "Effects of stress-induced mismatches on CMOS analog circuits," in Proc. Int. Symp. VLSI Technol., Syst., Appl., 1995, pp. 345-360.
35. J. Bastos, M. S. J. Steyaert, A. Pergoot, and W. M. Sansen, "Influence of die attachment on MOS transistor matching," IEEE Trans. Semicond. Manuf., vol. 10, no. 2, pp. 209-218, May 1997. (Pubitemid 127763251)
36. H. Tuinhout, M. Pelgrom, R. Penning de Vries, and M. Vertregt, "Effects of metal coverage on MOSFET matching," in Proc. Int. Electron Devices Meet., Dec. 1996, pp. 735-738.
37. A. Pavasovic, A. G. Andreou, and C. R.Westgate, "Characterization of subthreshold mismatch in transistors for VLSI systems," J. VLSI Signal Process., vol. 8, no. 1, pp. 75-85, 1994.
38. T. L. Tewksbury, III and L. Hae-Seung, "Characterization, modeling, and minimization of transient threshold voltage shifts in MOSFETs," IEEE J. Solid-State Circuits, vol. 29, no. 3, pp. 239-252, Mar. 1994.
39. W. Gao, D. Gao, D. Brasse, C. Hu-Guo, and Y. Hu, "Precise multiphase clock generation using low-jitter delay-locked loop techniques for positron emission emission tomography imaging," IEEE Trans. Nucl. Sci., vol. 57, no. 3, pp. 1063-1070, Jun. 2010.
40. W. Uhring, C.-V. Zint, P. Summ, and B. Cunin, "Very high long-term stability synchroscan streak camera," Rev. Scientif. Instrum., vol. 74, pp. 3313-3320, 2003.
41. E. Delagnes, D. Breton, F. Lugiez, and R. Rahmanifard, "A low power multi-channel single ramp ADC with up to 3.2 GHz virtual clock," IEEE Trans. Nucl. Sci., vol. 54, no. 5, pp. 1735-1742, Oct. 2007. (Pubitemid 47599147)