A multiphase-output delay-locked loop with a novel start-controlled phase/frequency detector

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 55, Issue 9, 2008, Pages 2483-2490

  Chang, Robert Chen Hao ^a   Chen, Hou Ming ^a   Huang, Po Jen ^a  

^a NATIONAL CHUNG HSING UNIVERSITY   (Taiwan)

Author keywords

Multiphase output delay locked loop; NAND resettable dynamic D flip flop; Phase frequency detector; Voltage controlled delay element

Indexed keywords

ELECTRIC POWER UTILIZATION; FLIP FLOP CIRCUITS; NAND CIRCUITS; PHASE COMPARATORS;

DELAY-LOCKED LOOPS; LOWER-POWER CONSUMPTION; MULTIPHASE-OUTPUT; MULTIPHASE-OUTPUT DELAY-LOCKED LOOP; NAND- RESETTABLE DYNAMIC D-FLIP-FLOP; PHASE/FREQUENCY DETECTOR; VOLTAGE-CONTROLLED DELAY ELEMENT; VOLTAGE-CONTROLLED DELAY LINES;

DELAY LOCK LOOPS;

EID: 56349113938     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2008.920088     Document Type: Article

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