Clock aligner based on delay locked loop with double edge synchronization

Microelectronics Reliability

Volumn 48, Issue 1, 2008, Pages 158-166

  Stojčev, Mile ^a   Jovanović, Goran ^a  

^a FACULTY OF ELECTRONIC ENGINEERING   (Serbia)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; SYNCHRONIZATION;

DELAY LOCKED LOOP; MULTISTAGE OUTPUT PULSES;

DELAY CIRCUITS;

EID: 39349105944     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2007.02.025     Document Type: Article

References (23)

1. Oklobdzija V., Stojanovic M., Markovic D., and Nedovic N. Digital system clocking: high-performance and low-power aspects (2003), Wiley Pub, Hoboken, New Jersey
2. Sapatnekar S. Timing (2004), Kluwer Academic Publishers, Boston
3. Johnson H., and Graham M. High-speed signal propagation: advanced black magic (2003), Prentice Hall, Upper Saddle River, NJ, 07458
4. Oklobdzija V.G. Clocking and clocked storage elements in a multi-gigahertz environment. IBM J Res Dev 47 5/6 (2003) 567-584
5. Razavi B. Phase-locking in high-performance systems: from devices to architectures (2003), Wiley Pub, Hoboken, New Jersey
6. Oklobdzija V., and Krisnamurthy R.-K. High-performance energy-efficient microprocessor design (2006), Springer, Boston
7. Kim C., and Kang S. A low-swing clock double-edge triggered flip-flop. IEEE J Solid-State Circ 37 5 (2002) 648-652
8. Mu F., and Svensson C. Pulse control loop in high-speed CMOS clock buffers. IEEE J Solid-State Circ 35 2 (2000) 134-141
9. Nedovic N, Aleksic M, Oklobdzija VG. Comparative analysis of double-edge versus single-edge triggered clocked storage elements. In: Proceedings of IEEE international symposium on circuits and systems. Scottsdale, Arizona; 2002. p. V105-8.
10. Nedovic N., and Oklobdzija V.G. Dual-edge triggered storage elements and clocking strategy for low-power systems. IEEE Trans VLSI Sys 13 5 (2005) 577-590
11. Advanced Computer Systems Engineering Laboratory (ACSEL), Low Power Clocking Project. .
12. Garlepp B., Donnelly K., Kim J., Chau P., Zerbe J., et al. A portable digital DLL for high-speed CMOS clock buffers. IEEE J Solid-State Circ 34 5 (1999) 632-643
13. Han S.-R., and Liu S.-I. A 500 MHz-1.25 GHz fast-locking pulsewidth control loop with presettable duty-cycle. IEEE J Solid-State Circ 39 3 (2004) 463-468
14. Yang P.-H., and Wang J.-S. Low voltage pulsewidth control loops for SoC applications. IEEE J Solid-State Circ 37 10 (2002) 1348-1351
15. Lin W.-M., and Huang H.-Y. A low-jitter mutual-correlated pulsewidth control loop Circuit. IEEE J Solid-State Circ 39 8 (2004) 1366-1369
16. Tu H.-L. A differential pulsewidth control loop for high-speed VLSI systems. IEEE Trans Circ Syst II 53 5 (2006) 417-421
17. Wang Y.-J., Kao S.-K., and Liu S.-I. All-digital delay-locked loop/pulsewidth-control loop with adjustable duty-cycles. IEEE J Solid-State Circ 41 6 (2006) 1262-1274
18. Maneatis J. Low-jitter process-independent DLL and PLL based on self-biased techniques. IEEE J Solid-State Circ 31 11 (1996) 1723-1732
19. Moon Y., Choi J., Lee K., Jeong D.-K., and Kim M.-K. An all-analog multiphase DLL using a replica delay line for wide-range operation and low-jitter performance. IEEE J Solid-State Circ 35 3 (2000) 377-384
20. Jovanović G., and Stojčev M. Current starved delay element with symmetric load. Int J Electron 93 3 (2006) 167-175
21. Kang S.-M., and Leblebici Y. CMOS digital integrated circuits: analysis and design. 3rd ed. (2003), Mc-Graw Hill, New York
22. Yuan J., and Svensson C. High-speed CMOS circuit technique. IEEE J Solid-State Circ 24 1 (1989) 62-70
23. Jovanović G, Stojčev M, Krstić D. Delay locked loop with linear delay element. In: Proceedings of seventh international conference. TELSIKS, Niš, Serbia; 2005. p. 397-400.